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A Cheat Sheet for the DesignWare Solutions for AMBA IP

AMBA™ 2.0 and AMBA 3 AXI™ are standard bus architectures developed by ARM and targeted for high-performance, high-frequency system designs. The DesignWare® IP solution for AMBA 2.0 and AMBA 3 AXI provides a portfolio of synthesizable IP to aid designers in the rapid and accurate development of AMBA 2.0 and AXI-based components and system-on-chip (SoC) designs. Each component is packaged using Synopsys coreTools to reduce integration risk and provide flexible, reliable configuration. Using synthesizable DesignWare AMBA IP enables designers to focus on the high value portion of their product, while significantly reducing time to market and development costs.

Component Overview

Infrastructure & Fabric
Component NameShort Description
DW_axi High performance, low latency interconnect fabric for AMBA 3 AXI
DW_axi_x2p High performance, low latency interconnect fabric and bridge for AMBA 2 & 3 APB for direct connect to AMBA 3 AXI fabric
DW_axi_rs Configurable standalone pipelining stage for AMBA 3 AXI subsystems
DW_ahb High performance, low latency interconnect fabric for AMBA 2 AHB
DW_ahb_icm Configurable multi-layer interconnection matrix
DW_apb High performance, low latency interconnect fabric & bridge for AMBA 2 APB for direct connect to AMBA 2 AHB fabric
DW_axi_x2h Bridge from AMBA 3 AXI to AMBA 2.0 AHB, enabling easy integration of legacy AHB designs with newer AXI systems
DW_axi_x2x Flexible bridge between multiple AMBA 3 AXI components or busses
DW_axi_hmx Configurable high performance interface from AHB master to an AXI slave
DW_ahb_h2h Area efficient, low bandwidth AMBA 2 AHB to AHB Bridge
DW_ahb_eh2h High performance, high bandwidth AMBA 2 AHB to AHB bridge
DW_axi_gm Simplify the connection of third party/custom master controllers to any AMBA 3 AXI fabric
DW_axi_gs Simplify the connection of third party/custom slave controllers to any AMBA 3 AXI fabric
DW_ahb_ictl Configurable vectored interrupt controllers for AHB bus systems
DW_apb_ictl Configurable vectored interrupt controllers for APB bus systems
DMA
Component NameShort Description
DW_ahb_dmac A flexible, multi channel, multi interface, centralized DMA controller for the AHB bus protocol
DDR1/SDRAM/SRAM Memory Controller
Component NameShort Description
DW_memctl A highly flexible interface from many popular memory standards to an AMBA 2 AHB bus
APB General Peripherals
Component NameShort Description
DW_apb_gpio General Purpose I/O pad control peripheral for the AMBA 2 APB bus
DW_apb_timersConfigurable system counters, controlled through an AMBA 2 APB interface
DW_apb_rtc A configurable high range counter with an AMBA 2 APB slave interface
DW_apb_rap Programmable controller for the remap and pause features of the DW_ahb interconnect
DW_apb_wdt A programmable watchdog timer peripheral for the AMBA 2 APB bus
APB Advanced Peripherals
Component NameShort Description
DW_apb_ssi A configurable, programmable, full-duplex, master or slave synchronous serial interface
DW_apb_i2c A highly configurable, programmable master or slave i2c device with an APB slave interface
DW_apb_i2s A configurable master or slave device for the three-wire interface (I2S) for streaming stereo audio between devices
DW_apb_uart A programmable and configurable Universal Asynchronous Receiver/Transmitter (UART) for the AMBA 2 APB bus

Infrastructure & Fabric

The DesignWare Infrastructure and Fabric components for AMBA 2 and AMBA 3 AXI includes all the essential building blocks for AMBA 2 and AMBA 3 AXI based subsystem topologies. The components are highly configurable providing the design engineer the flexibility to tailor the components to their desired design requirements. Comprehensive subsystems can be quickly assembled using coreAssembler, an included graphical based subsystem assembly tool. coreAssembler automates the subsystem assembly and IP configuration which includes the creation of an initial verification testbench environment enabled by DesignWare Verification IP, thus significantly reducing the time to first simulation.

The DesignWare Fabric components for AMBA are available in encrypted format as part of the DesignWare Library. RTL source code is licensed separately on a pay-per-use basis as part of the DWC AMBA Fabric license package.

  • High performance, low latency interconnect fabric for AMBA 3 AXI -> DW_axi
    • Multiple address multiple data architecture for maximum bandwidth utilization.
    • Advanced internal pipelining options, up to 2 separate pipeline stages per channel for high frequency operation.
    • Master/Slave visibility to reduce area and increase performance.
    • Range of arbitration options for each channel, from priority based arbitration to fair arbitration schemes.
    • Full ID ordering model support. Multiple outstanding transactions with different ID's from each master.
    • Support for write data from different masters to be interleaved to slaves.
    • Bi-Directional command support for multi-interconnected subsystems.

  • High performance, low latency interconnect fabric and bridge for AMBA 2 & 3 APB for direct connect to AMBA 3 AXI fabric -> DW_axi_x2p
    • Provides full APB master functionality, APB slave decoding and multiplexing.
    • Configurable buffer depths for bus offloading.
    • Performs data consistency checking, with AXI error generation.
    • Downsizes larger AXI data beats to smaller APB data busses.
    • Supports both AMBA 2.0 and 3.0 APB slaves.
    • Comprehensive clocking options with configurable synchronization depths.
    • Configurable data endianness translation.

  • Configurable standalone pipelining stage for AMBA 3 AXI subsystems -> DW_axi_rs
    • Provides timing isolation on any AXI connection with no throughput penalty.
    • User configurable to pipeline forward, backward or all channel paths.
    • Flexibility to pipeline only the desired AXI channels.

  • High performance, low latency interconnect fabric for AMBA 2 AHB -> DW_ahb
    • Full protocol support, split, retry, early burst termination and more.
    • Advanced programmable arbitration options. From priority based to fair arbitration to guaranteed QOS (weighted token).
    • Configurable system endianness, static or dynamically controlled.
    • Support for memory remap and contiguous or non-contiguous slave memory regions.
    • Configurable support for undefined length bursts or undefined length burst termination.
    • Additional AMBA-lite mode optimizes fabric for single master systems.

  • Configurable multi-layer interconnection matrix -> DW_ahb_icm
    • Allows up to 8 AHB layers to access a common AHB slave.
    • Full protocol support, split capable slave, AHB locking and more.
    • Starvation prevention features, RETRY issued to layers waiting longer than a configured time limit.
    • Static layer arbitration scheme. External layer priorities supported.

  • High performance, low latency interconnect fabric & bridge for AMBA 2 APB for direct connect to AMBA 2 AHB fabric -> DW_apb
    • Supports up to 16 APB slaves.
    • Matches a larger AHB data width to a smaller APB data width.
    • Supports an AHB clock with is an integer multiple of the APB clock.
    • Configurable support for an external decoder.

  • Bridge from AMBA 3 AXI to AMBA 2.0 AHB, enabling easy integration of legacy AHB designs with newer AXI systems -> DW_axi_x2h
    • Large range of configurable buffer depths for bus offloading.
    • Supports data downsizing from a larger AXI bus to a smaller AHB bus.
    • Configurable clock domain crossing, optimized for asynchronous, synchronous or single clock operation.
    • Provides pipelining options for high frequency operation.
    • Additional AHB-lite mode enables optimizations for single master AHB subsystems.
    • Configurable data endianness translation.

  • Flexible bridge between multiple AMBA 3 AXI components or busses -> DW_axi_x2x
    • Large range of configurable buffer depths for bus offloading.
    • Data widths of up to 512 on either interface with full translation between them.
    • Option to perform data upsizing going from a smaller to larger data width.
    • Low latency operation with pipelining options for high performance.
    • Comprehensive clocking options with configurable synchronization depths.
    • Full ID ordering model support, with both read and write interleaving and reordering supported at both interfaces.
    • Configurable number of multiple outstanding transactions.

  • Configurable high performance interface from an AHB master to an AXI slave -> DW_axi_hmx
    • Buffered writes for high performance.
    • Static or dynamic transaction blocking for transaction ordering enforcement.
    • Configurable AHB to AXI endianness conversion.
    • Support for slower synchronous AHB clock.
    • Multiple pipelining options for high frequency operation.

  • Area efficient, low bandwidth AMBA 2 AHB to AHB Bridge -> DW_ahb_h2h
    • Performs data bus downsizing.
    • Comprehensive clocking options and clock domain crossing for both synchronous and asynchronous clocks.
    • Very low gate count implementation, as low as 2K for a minimum configuration.
    • Configurable data endianness translation.
    • Additional AHB-lite mode enables optimizations for single master systems.

  • High performance, high bandwidth AMBA 2 AHB to AHB bridge -> DW_ahb_eh2h
    • Large range of channel buffer depths for bus offloading.
    • Statically or dynamically controllable split generation from the slave interface to free bus cycles until resources available.
    • Pre-fetched read data, returned on split completion.
    • Asynchronous or synchronous clocks on both interfaces.
    • Posted writes with interrupt generation on write error responses.
    • Pipelining options for high frequency performance.

  • Simplify the connection of third party/custom master controllers to any AMBA 3 AXI fabric -> DW_axi_gm
    • Translates from a generic request and response channel to the 5 channel AXI interface.
    • Low latency operation with 100% throughput efficiency.
    • Provides pipelining options to ease timing closure.
    • Configurable to allow transactions to be blocking or non-blocking.
    • Support for different synchronous clocks on each interface.

  • Simplify the connection of third party/custom slave controllers to any AMBA 3 AXI fabric -> DW_axi_gs
    • Low latency operation with 100% throughput efficiency.
    • Provides pipelining options to ease timing closure.
    • Generic interface lite mode to interface with simple slaves e.g. an SRAM.
    • Ability to monitor multiple AXI exclusive accesses.
    • Support for different synchronous clocks on each interface.

  • Configurable vectored interrupt controllers for AHB or APB bus systems -> DW_ahb_ictl / DW_apb_ictl
    • Separate peripherals, 1 with an AHB slave interface, 1 with an APB slave interface.
    • Up to 64 normal interrupt sources, and 8 fast interrupt sources.
    • Combinatorial interrupt processing, interrupts propagate without clock running.
    • Interrupts can be enabled, masked, forced (software interrupts) and software sampled at all stages.
    • Priority based interrupt filtering, with support for programmable interrupt source priorities.
    • Vectored interrupt generation.

DMA

The DesignWare DMA controller is a highly optimized centralized DMA IP component offering configuration of up to 8 channels each with dedicated channel buffers. The DesignWare DMA component can be configured and instantiated into the subsystem using coreAssembler, an included graphical based subsystem assembly tool. coreAssembler automates the subsystem assembly and IP configuration which includes the creation of an initial verification testbench environment enabled by DesignWare Verification IP, thus significantly reducing the time to first simulation.

The DesignWare DMA component for AMBA is available in encrypted format as part of the DesignWare Library. RTL source code is licensed separately, on a pay-per-use basis as part of the DWC DMA Controller license package.

  • A flexible, multi channel, multi interface, centralized DMA controller for the AHB bus protocol -> DW_ahb_dmac
    • Configurable selection of up to 8 DMA channels width dedicated channel buffering.
    • Up to 4 AHB master interfaces with support for operation across multiple AHB layers.
    • Flexible handshaking options, software based, hardware based or peripheral interrupt based.
    • Features for improved bandwidth utilization e.g. bus locking, interface locking, fifo level mode.
    • Dedicated AHB slave interface for programmable DMA control.
    • Ability to allow source, destination or DW_ahb_dmac to enforce flow control.
    • Powerful address generation options e.g. multi DMA blocks, linked lists, auto channel register reloading.

DDR1/SDRAM/SRAM Memory Controller

The DesignWare Memory Controller is a multi-purpose memory controller supporting a wide variety of standard memory devices. Configuration flexibility provides the designer with the choice of either a single memory interface or both dynamic and static memory interfaces in one controller. The DesignWare Memory Controller component can be configured and instantiated into the subsystem using coreAssembler, an included graphical based subsystem assembly tool. coreAssembler automates the subsystem assembly and IP configuration which includes the creation of an initial verification testbench environment enabled by DesignWare Verification IP, thus significantly reducing the time to first simulation.

The DesignWare Memory Controller component for AMBA is available in encrypted format as part of the DesignWare Library. RTL source code is licensed separately, on a pay-per-use basis as part of the DWC Memory Controller license package.

  • A highly flexible interface from many popular memory standards to an AMBA 2 AHB bus -> DW_memctl
    • Support for SDR-SDRRAM, Mobile SDR-SDRAM, Mobile DDR-SDRAM, DDR-SDRAM, asynchronous SRAM and asynchronous FLASH.
    • As an SDRAM controller, supports 16 row address bits, 15 column address bits and 4 bank address bits.
    • As a static memory controller, supports up to 32 address bits.
    • Allows up to 8 groups of external memory connected to a single chip select.

APB General Peripherals

The DesignWare APB General Peripheral components include many of the commonly used AMBA Peripheral bus building blocks. The components are highly configurable providing the design engineer the flexibility to tailor the components to their desired design requirements. Comprehensive subsystems can be quickly assembled using coreAssembler, an included graphical based subsystem assembly tool. coreAssembler automates the subsystem assembly and IP configuration which includes the creation of an initial verification testbench environment enabled by DesignWare Verification IP, thus significantly reducing the time to first simulation.

The DesignWare APB General Peripheral components for AMBA are available in encrypted format as part of the DesignWare Library. RTL source code is licensed separately, on a pay-per-use basis as part of the DWC APB Peripherals license package.

  • General Purpose I/O pad control peripheral for the AMBA 2 APB bus -> DW_apb_gpio
    • Support for up to 128 individually configurable signals.
    • Configurable hardware and software control of each signal.
    • Allows memory mapped reading of external I/O port signals.
    • Optional de-bounce logic and metastability synchronization registers.
    • Configurable selection of external ports as interrupt sources.

  • Configurable system counters, controlled through an AMBA 2 APB interface -> DW_apb_timers
    • Up to 8 counters with individually configurable widths and programmable reload values.
    • Option to drive counters from asynchronous clocks, with full synchronization performed.
    • Fully featured interrupt interface with configurable interrupt pulse extension.

  • A configurable high range counter with an AMBA 2 APB slave interface -> DW_apb_rtc
    • Supports a count width up to 32 bits.
    • Allows a unique counter clock which may be fully asynchronous with system clock.
    • Read coherency registers for accurate count value sampling.
    • Features interrupt generation from a configurable clock domain.

  • Programmable controller for the remap and pause features of the DW_ahb interconnect -> DW_apb_rap
    • Allows safe programmable control of the remap feature of the DW_ahb.
    • Supports forcing the DW_ahb bus into a low power mode with the pause feature.
    • Performs reset signal monitoring on a configurable number of interrupts.

  • A programmable watchdog timer peripheral for the AMBA 2 APB bus -> DW_apb_wdt
    • Programmable timer width and timeout value.
    • Programmable reset pulse or interrupt generation on timeout event.
    • Support for an external clock to drive the timeout counter.
    • Prevents accidental counter restarting and device disabling.

APB Advanced Peripherals

The DesignWare APB Advanced Peripheral components include many of the industries commonly used interface IPs. The components are highly configurable providing the design engineer the flexibility to tailor the components to their desired design requirements. Comprehensive subsystems can be quickly assembled using coreAssembler, an included graphical based subsystem assembly tool. coreAssembler automates the subsystem assembly and IP configuration which includes the creation of an initial verification testbench environment enabled by DesignWare Verification IP, which significantly reduces the time to first simulation.

The DesignWare APB Advanced Peripheral components for AMBA are available in encrypted format as part of the DesignWare Library. RTL source code is licensed separately, on a pay-per-use basis as part of the DWC APB Advanced Peripherals license package.

  • A configurable, programmable, full-duplex, master or slave synchronous serial interface -> DW_apb_ssi
    • Features an APB slave interface.
    • Supports the SPI, SSP and Microwire serial protocols, with static or programmable protocol selection.
    • Configurable transmit and receive fifo depths.
    • Generic hardware DMA controller interface, with programmable fifo threshold levels.
    • Supports synchronous or asynchronous APB clock and serial clock.

  • A highly configurable, programmable master or slave i2c device with an APB slave interface -> DW_apb_i2c
    • Supports all I2C speed modes, Standard (100Kb/s), Fast (400Kb/s) and High Speed (3.4Mb/s).
    • Support for both 7 and 10 bit addressing.
    • Configurable transmit and receive buffer depths.
    • Handles bit and byte waiting at all bus speeds.
    • Includes a generic DMA hardware handshaking interface, compatible with the DW_ahb_dmac.

  • A configurable master or slave device for the three-wire interface (I2S) for streaming stereo audio between devices -> DW_apb_i2s
    • Operates as an i2s transmitter and or receiver.
    • Configurable support for up to 4 stereo channels for both transmitter and receiver.
    • Programmable audio data resolutions from 12 to 32 bits.
    • Configurable fifo depths with programmable threshold values.
    • Comprehensive clocking options, synchronous and asynchronous APB and I2S clocks supported.

  • A programmable and configurable Universal Asynchronous Receiver/Transmitter (UART) for the AMBA 2 APB bus -> DW_apb_uart
    • 16750 compatible auto-flow control supported to increase system efficiency and reduce software load.
    • Option to include configurable transmit and receive fifos with programmable threshold levels for interrupt generation.
    • Generic DMA hardware handshaking interface, compatible with DW_ahb_dmac.
    • Serial infrared supported.
    • Advanced diagnostic capabilities with a modem control loopback mode.
    • Supports asynchronous pclk and serial baud clock with full synchronization.

Licenses

The DesignWare synthesizable IP components for AMBA/AXI require a DesignWare license to create configured, encrypted RTL for verification or synthesis using DesignWare coreAssembler or coreConsultant. In order for you to create unencrypted RTL source, you must have the source license for the specific component, as shown in the table below.

License Requirements for DesignWare Synthesizable IP for AMBA/AXI