Synopsys DDR multiPHY IP Datasheet

Download the Synopsys DDR multiPHY IP datasheet and see how a GDSII-based hard PHY delivers LPDDR2, mDDR, DDR2, DDR3, DDR3L, and DDR3U support—optimized for up to 1066Mbps, low power, and rapid integration with Synopsys memory controllers.

What You Will Learn:

• How to implement a hard PHY supporting LPDDR2 (533MHz), DDR3/3L/3U/DDR2 (1066Mbps), and mDDR
• Multi-protocol I/Os: programmable drive strength, ODT, wire bond/CUP/flip chip compatibility, and ESD protection
• Integration: DFI 2.1 interface, GDSII delivery, rapid hookup to Synopsys Universal DDR controllers, and flexible channel width
• Signal integrity: PVT-compensated I/Os, low-jitter DLLs, dynamic drift detection/compensation, and precise DQS timing