Building Block IP Downloads

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System-Level Design High-level block design, architecture design, virtual and FPGA-based prototyping, and, power electronics and wiring harness solutions		Manufacturing Mask synthesis and data prep, lithography simulation and verification and yield management

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Interface IP Standard interfaces for SoC designs such as USB, PCIe, DDR, SATA, HDMI, MIPI, Ethernet and more		Processor IP ARC processor cores and extensions, ARC audio, and ARC development tools, operating systems & ecosystem

Analog IP Analog IP such as audio analog codecs, data converters and video analog front-end		SoC Infrastructure IP minPower Components, Verification IP and the DesignWare Library including datapath IP, AMBA, foundry libraries and 8-bit microcontrollers

Memories and Logic Libraries Logic libraries, memory compilers and non-volatile memories optimized for performance, power and area. Memory test and repair for higher test quality & yield		IP Subsystems Pre-verified audio subsystem integrating hardware, software and prototyping

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High-Level Block Design Rapidly create and optimize differentiated IP blocks with Algorithm Design and Analysis, High-Level Synthesis, and Processor Development		Virtual Prototyping Accelerate pre-RTL embedded software development, hardware/software integration, and system validation

Architecture Design Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design		FPGA-Based Prototyping Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow

Power Electronic Systems Simulate and execute behavioral design, modeling, and simulation for power electronics, multi-domain systems, and wire harnesses		System-Level Models Reduce risk and speed time to market with pre-verified models supporting industry standards for interoperability

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IP Integration & SoC Verification Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification		FPGA-based Prototyping Improve time-to-market and avoid costly re-spins

Solutions for Semiconductor and System Design


End-to-End Solutions Comprehensive solutions: Advanced Low Power Solution, System-to-Silicon (S2S) Verification Solution, 3D-IC Design Solutions		Technical Platforms Integrated product platforms: Discovery Verification Platform, FPGA Design Solution, Galaxy Implementation Platform

Industry Solutions Tailored solutions for automotive, memory, mil/aero, mobile devices, & end-product categories		Lynx Design System A highly integrated, production-ready IC development platform

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Building Block IP Downloads

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Spotlight

DesignWare Electronic Software Transfer (EST)
For Building Block ("Foundation") Components

Synopsys provides for the electronic transfer of the continuously enhanced and expanded DesignWare Library Building Block IP. There are quarterly Electronic Software Transfer (EST) releases in addition to our regular train releases each year.

DesignWare Building Block IP for DC

January 2011 EST Release (DWBB_1101)

Download for Design Compiler D-2010.03 Release

Download for Design Compiler C-2009.06 Release

April 2010 EST Release (DWBB_1004)

Download for Design Compiler D-2010.03 Release

Download for Design Compiler C-2009.06 Release

Download for Design Compiler B-2008.09 Release

February 2009 EST Release (DWBB_0902)

Download for Design Compiler B-2008.09 Release

Download for Design Compiler A-2007.12 Release

Download for Design Compiler Z-2007.03 Release

October 2008 EST Release (DWBB_0810)

Download for Design Compiler B-2008.09 Release

Download for Design Compiler A-2007.12 Release

Download for Design Compiler Z-2007.03 Release

April 2008 EST Release (DWBB_0803)

Download for Design Compiler A-2007.12 Release

Download for Design Compiler Z-2007.03 Release

Download for Design Compiler Y-2006.06 Release

DesignWare Building Block IP for VCSMX

January 2011 EST Release (DWBB_1101)

Download for VCSMX 2006.06 and later

April 2010 EST Release (DWBB_1004)

Download for VCSMX 2006.06 and later

February 2009 EST Release (DWBB_0902)

Download for VCSMX 2006.06 and later

October 2008 EST Release (DWBB_0810)

Download for VCSMX 2006.06 and later

April 2008 EST Release (DWBB_0803)

Download for VCSMX 2006.06 and later

Other Downloads

Retrieve EST releases for other Synopsys products

Notes for EST Download

Located in the Release Notes for this EST release, users will find instructions on how to run reanalysis scripts. Located within the /dw/scripts/ root directory, these scripts are installed as part of this EST. Upon execution, these scripts will analyze all existing Building Block components within your /dw/ tree to ensure compatibility with the latest versions of Synopsys Synthesis and/or VHDL simulation tool releases. You will need to run these scripts after have installed a newer version of Synopsys Synthesis or VCS MX and you have installed this EST release. Executing these scripts requires write permission to the Synopsys tools directory tree.

For details, please refer to the instructions located in the Release Notes.

For more information on the DesignWare Library or the extensive implementation and verification IP offerings from the DesignWare family of products, please visit the DesignWare home page.

For Assistance:

Download Problems: designware@synopsys.com
Other Problems: support_center@synopsys.com