The DesignWare Memory controller is a multi-purpose memory controller supporting a wide variety of standard memory devices. Configuration flexibility provides the designer with the choice of either a single memory interface or both dynamic and static memory interfaces in one controller.The DesignWare Memory controller component can be configured and instantiated into the subsystem using coreAssembler, an included graphical based subsystem assembly tool. coreAssembler automates the subsystem assembly and IP configuration which includes the creation of an initial verification testbench environment enabled by DesignWare Verification IP, thus reducing the time to first simulation.
The DesignWare memory controller component for AMBA is available in encrypted format as part of the DesignWare Library. RTL source code is available for license separately, on a pay-per-use basis as part of the DWC Memory Controller license package.
|Configurable SDR-SDRAM, DDR-SDRAM, SRAM & Flash Memory Controller (DW_memctl)|
- Support for SDR-SDRAM, Mobile SDR-SDRAM, Mobile DDR-SDRAM, DDR-SDRAM, asynchronous SRAM and asynchronous FLASH.
- As an SDRAM controller, supports 16 row address bits, 15 column address bits and 4 bank address bits.
- As a static memory controller, supports up to 32 address bits.
- Allows up to 8 groups of external memory connected to a single chip select.
|Verification IP for AMBA 2 AHB|
- DesignWare Verification IP integrates easily into Verilog, SystemVerilog, VHDL and OpenVera testbenches to generate bus traffic and check for protocol violations. Monitors provide extensive reports to show functional coverage of the bus protocols.
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