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DesignWare IP Solutions for AMBA - Infrastructure & Fabric

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The DesignWare® Infrastructure and Fabric components for AMBA® 2.0, AMBA 3 AXI™, and AMBA 4 AXI with ACE-Lite support include all the essential building blocks for almost all AMBA-based subsystem topologies, including AMBA 2, AMBA 3 AXI, and AMBA 4 AXI. The components are highly configurable, providing designers with the flexibility to tailor the components to their design requirements. Comprehensive subsystems can be quickly assembled using coreAssembler, an included graphical based subsystem assembly tool. coreAssembler automates the subsystem assembly and IP configuration which includes the creation of an initial verification testbench environment enabled by DesignWare Verification IP, thus reducing the time to first simulation.

The DesignWare Fabric components for AMBA are available in encrypted format as part of the DesignWare Library. RTL source code with additional differentiated features is available for license separately, on a pay-per-use basis as part of the DesignWare Cores AMBA Fabric license package. The AMBA infrastructure and fabric solution consists of the following:

High-performance, low-latency interconnect fabric for AMBA 3 AXI and AMBA 4 AXI (DW_axi)
  • Hybrid architecture reduces area, power consumption, and routing congestion. Download white paper.
  • Multiple address, multiple data architecture for maximum bandwidth utilization
  • Advanced internal pipelining options with up to 2 separate pipeline stages per channel for high frequency operation
  • Master/slave visibility to reduce area and increase performance
  • Arbitration options for each channel offer priority-based arbitration to fair arbitration schemes
  • Full ID ordering model support. Multiple outstanding transactions with different IDs from each master
  • Support for write data from different masters to be interleaved to slaves
  • Bi-directional command support for multi-interconnected subsystems
  • ACE-Lite support with a simple configuration
High-performance, low-latency interconnect fabric and bridge for AMBA 2 and 3 APB for direct connect to AMBA 3 AXI/AMBA 4 AXI fabric (DW_axi_x2p)
  • Provides full APB master functionality, APB slave decoding, and multiplexing
  • Configurable buffer depths for bus offloading
  • Performs data consistency checking with AXI error generation
  • Downsizes larger AXI data beats to smaller APB data busses
  • Supports both AMBA 2.0 and 3.0 APB slaves
  • Comprehensive clocking options with configurable synchronization depths
  • Configurable data endianness translation
  • ACE-Lite support
Configurable standalone pipelining stage for AMBA 3 AXI/AMBA 4 AXI subsystems (DW_axi_rs)
  • Provides timing isolation on any AXI connection with no throughput penalty
  • User configurable to pipeline forward, backward or all channel paths
  • Flexibility to pipeline only the desired AXI channels
  • ACE-Lite support
High-performance, low-latency interconnect fabric for AMBA 2 AHB (DW_ahb)
  • Full protocol support, split, retry, early burst termination, and more
  • Advanced programmable arbitration options, from priority-based, to fair arbitration, to guaranteed QOS (weighted token)
  • Configurable system endianness, static or dynamically controlled
  • Support for memory remap and contiguous or non-contiguous slave memory regions
  • Configurable support for undefined length bursts or undefined length burst termination
  • Additional AMBA-lite mode optimizes fabric for single master systems
Configurable multi-layer interconnection matrix (DW_ahb_icm)
  • Allows up to 8 AHB layers to access a common AHB slave
  • Full protocol support, split capable slave, AHB locking and more
  • Starvation prevention features, RETRY issued to layers waiting longer than a configured time limit
  • Static layer arbitration scheme with external layer priorities supported
High-performance, low-latency interconnect fabric and bridge for AMBA 2 APB for direct connect to AMBA 2 AHB fabric (DW_apb)
  • Supports up to 16 APB slaves
  • Matches a larger AHB data width to a smaller APB data width
  • Supports an AHB clock with is an integer multiple of the APB clock
  • Configurable support for an external decoder
Bridge from AMBA 3 AXI/AMBA 4 AXI to AMBA 2.0 AHB, enabling easy integration of legacy AHB designs with newer AXI systems (DW_axi_x2h)
  • Large range of configurable buffer depths for bus offloading
  • Supports data downsizing from a larger AXI bus to a smaller AHB bus
  • Configurable clock domain crossing, optimized for asynchronous, synchronous, or single clock operation
  • Provides pipelining options to for high-frequency operation
  • Additional AHB-lite mode enables optimizations for single master AHB subsystems
  • Configurable data endianness translation
  • ACE-Lite support
Flexible bridge between multiple AMBA 3 AXI/AMBA 4 AXI components or busses (DW_axi_x2x)
  • Large range of configurable buffer depths for bus offloading
  • Data widths of up to 512 on either interface with full translation between them
  • Option to perform data upsizing going from a smaller to larger data width
  • Low-latency operation with pipelining options for high performance
  • Comprehensive clocking options with configurable synchronization depths
  • Full ID ordering model support, with both read and write interleaving and reordering supported at both interfaces
  • Configurable number of multiple outstanding transactions
  • ACE-Lite support
Configurable high-performance interface from and AHB master to an AXI slave (DW_axi_hmx)
  • Buffered writes for high performance
  • Static or dynamic transaction blocking for transaction ordering enforcement
  • Configurable AHB to AXI endianness conversion
  • Support for slower synchronous AHB clock
  • Multiple pipelining options for high-frequency operation
Area-efficient, low-bandwidth AMBA 2 AHB to AHB bridge (DW_ahb_h2h)
  • Performs data bus downsizing
  • Comprehensive clocking options and clock domain crossing for both synchronous and asynchronous clocks
  • Very low gate count implementation (as low as 2K for a minimum configuration)
  • Configurable data endianness translation
  • Additional AHB-lite mode enables optimizations for single master systems
High-performance, high-bandwidth AMBA 2 AHB to AHB bridge (DW_ahb_eh2h)
  • Large range of channel buffer depths for bus offloading
  • Statically or dynamically controllable split generation from the slave interface to free bus cycles until resources available
  • Pre-fetched read data, returned on split completion
  • Asynchronous or synchronous clocks on both interfaces
  • Posted writes with interrupt generation on write error responses
  • Pipelining options for high-frequency performance
Simplified connection of third-party/custom master controllers to the AMBA 3 AXI fabric (DW_axi_gm)
  • Translates from a generic request and response channel to the 5-channel AXI interface
  • Low-latency operation with 100% throughput efficiency
  • Provides pipelining options to ease timing closure
  • Configurable to allow transactions to be blocking or non-blocking
  • Support for different synchronous clocks on each interface
  • ACE-Lite support
Simplified connection of third-party/custom slave controllers to the AMBA 3 AXI fabric (DW_axi_gs)
  • Low-latency operation with 100% throughput efficiency
  • Provides pipelining options to ease timing closure
  • Generic interface lite mode to interface with simple slaves, e.g., an SRAM
  • Ability to monitor multiple AXI exclusive accesses
  • Support for different synchronous clocks on each interface
  • ACE-Lite support
Configurable vectored interrupt controllers for AHB or APB bus systems (DW_ahb_ictl / DW_apb_ictl)
  • Separate peripherals, 1 with an AHB slave interface, 1 with an APB slave interface
  • Up to 64 normal interrupt sources, and 8 fast interrupt sources
  • Combinatorial interrupt processing, interrupts propagate without clock running
  • Interrupts can be enabled, masked, forced (software interrupts) and software sampled at all stages
  • Priority-based interrupt filtering, with support for programmable interrupt source priorities
  • Vectored interrupt generation
Configurable bridge between an AHB or AXI bus protocol and an AXI bus protocol (DW_axi_a2x)
  • Complies with the AMBA 3 AXI, AMBA 4 AXI, ACE-Lite, and AMBA AHB specifications
  • Supports asynchronous, synchronous, and quasi-synchronous clocking
  • Provides asynchronous timing mode options to ease clock domain crossing
  • Configurable buffer depth for address and data channels
  • Configurable store and forward or cut-through mode
  • Configurable address port widths of any range from 32 to 64
  • Configurable data bus widths of 8, 16, 32 64, 128, 256, 512 bits
  • Support for transaction down-sizing (larger AHB/AXI bus to smaller AXI bus)
  • Dynamic controllable support for transaction up-sizing (smaller AHB/AXI bus to larger AXI bus)
  • Provides support for read data interleaving
  • Support for sideband/user signals
Verification IP for AMBA 2 AHB/APB, AMBA 3 AXI/AMBA 4 AXI

    Synopsys Discovery Verification IP (VIP) for ARM AMBA interfaces provides a comprehensive set of protocol, methodology, verification, and productivity features enabling users to rapidly achieve verification convergence on their AMBA-based designs.

    Discovery VIP for AMBA 4 is integrated with the Discovery Protocol Analyzer, a protocol-centric debug environment that gives users an easy-to-understand, graphical view of verification results. Discovery VIP for AMBA 4 is written entirely in SystemVerilog to run natively in the simulator for optimum performance.

  • Complete protocol support for AXI3, AXI4, AXI4-Lite, AXI4-Stream, ACE, ACE-Lite, AHB and APB
  • System and port level protocol checks for AXI3/4/Lite, AXI4-Stream and ACE/ACE-Lite, AHB and APB protocols
  • Built-in functional coverage and verification plans
  • Built-in UVM sequence library
  • Performance checking for latency and throughput
  • Configurable interconnect model
  • Backdoor access to ACE master cache
  • Integrated with Protocol Analyzer, a protocol-aware debug environment
  • Debug port for transaction tracking on waveform
  • Methodology support for VMM, UVM, OVM, and Verilog testbenches
  • Extensive callbacks, messaging, and functional coverage
  • Includes Reference Verification Platform for easy configuration and setup

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