The DesignWare APB Advanced Peripheral components include many of the industries commonly used interface IP's. The components are highly configurable providing the design engineer the flexibility to tailor the components to their desired design requirements. Comprehensive subsystems can be quickly assembled using coreAssembler, an included graphical based subsystem assembly tool. coreAssembler automates the subsystem assembly and IP configuration which includes the creation of an initial verification testbench environment enabled by DesignWare Verification IP, thus reducing the time to first simulation.
The DesignWare APB Advanced Peripheral components for AMBA are available in encrypted format as part of the DesignWare Library. RTL source code is available for license separately, on a pay-per-use basis as part of the DWC APB Advanced Peripherals license package.
|Configurable, programmable, full duplex, master or slave synchronous serial interface (SSI) (DW_apb_ssi)|
- Features an APB slave interface.
- Supports the SPI, SSP and Microwire serial protocols, with static or programmable protocol selection.
- Configurable transmit and receive fifo depths.
- Generic hardware DMA controller interface, with programmable fifo threshold levels.
- Supports synchronous or asynchronous APB clock and serial clock.
|Highly configurable, programmable master or slave i2c device with an APB slave interface (DW_apb_i2c)|
- Supports all I2C speed modes, Standard (100Kb/s), Fast (400Kb/s) and High Speed (3.4Mb/s).
- Support for both 7 and 10 bit addressing.
- Configurable transmit and receive buffer depths.
- Handles bit and byte waiting at all bus speeds.
- Includes a generic DMA hardware handshaking interface, compatible with the DW_ahb_dmac.
|Configurable master or slave device for the three-wire interface (I2S) for streaming stereo audio between devices (DW_apb_i2s)|
- Operates as an i2s transmitter and or receiver.
- Configurable support for up to 4 stereo channels for both transmitter and receiver.
- Programmable audio data resolutions from 12 to 32 bits.
- Configurable fifo depths with programmable threshold values.
- Comprehensive clocking options, synchronous and asynchronous APB and I2S clocks supported.
|A programmable and configurable Universal Asynchronous Receiver/Transmitter (UART) for the AMBA 2 APB bus (DW_apb_uart)|
- 16750 compatible auto-flow control supported to increase system efficiency and reduce software load.
- Option to include configurable transmit and receive fifos with programmable threshold levels for interrupt generation.
- Generic DMA hardware handshaking interface, compatible with DW_ahb_dmac.
- Serial infrared supported.
- Advanced diagnostic capabilities with a modem control loopback mode.
- Supports asynchronous pclk and serial baud clock with full synchronization
|Verification IP for AMBA 2 AHB/APB and AMBA 3 AXI|
- SystemVerilog, VHDL and OpenVera testbenches to generate bus traffic and check for protocol violations. Monitors provide extensive reports to show functional coverage of the bus protocols.
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