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A Unified Solution for Cell-based and Custom Design

Synopsys provides a unified solution for cell-based and custom designs, thereby enhancing SoC design efficiency and productivity. It is the first custom implementation solution built on an open architecture supporting interoperable process design kits (iPDKs) from leading foundries. Synopsys’ custom design solution delivers unmatched productivity with a common use model for simulation, analysis, parasitic extraction and physical verification.

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Custom Compiler-Visually-assisted Automation for Custom Layout
Learn about Synopsys' new full-custom solution that features a visually-assisted automation flow tuned for FinFET-based designs to speed up common design tasks, reduce iterations and enable reuse.
Chris Shaw, Technical Marketing Manager, Synopsys Fred Sendig, Synopsys Fellow, Synopsys

Improving Analog Verification Productivity Using Synopsys Simulation and Analysis Environment (SAE)
Learn about the comprehensive GUI-based transistor-level simulation and analysis environment that is deeply integrated with CustomSim, FineSim, and HSPICE circuit simulators.
Deepa Kannan, SAE Technical Marketing Manager, Synopsys

HSPICE Tips & Tricks Webisode Series
Learn from Synopsys applications engineers how to get the most out of HSPICE analysis. Topics will include how to most effectively use S-element, eye diagrams, IBIS-AMI, RUNLVL, and more. New mini webinars will premiere monthly.
Ted Mido, Principal Engineer, HSPICE R&D, Synopsys

Retrieving Data

Mini Demo: Laker Schematic-Driven Layout — Part 1
SDL methodology brings many benefits, but adoption has lagged because of the restrictions it sometimes places on layout flexibility. Laker’s next-generation SDL methodology is much more flexible, providing Laker users with the productivity benefits of SDL without sacrificing area.

Part 1 shows an intuitive schematic-driven layout solution that enables layout designers to optimize layout density through flexible, hierarchical device-level manipulation. Unlike competing tools, Laker does not require the layout and schematic hierarchies to match.

Mini Demo: Laker Schematic-Driven Layout — Part 2
SDL methodology brings many benefits, but adoption has lagged because of the restrictions it sometimes places on layout flexibility. Laker’s next-generation SDL methodology is much more flexible, providing Laker users with the productivity benefits of SDL without sacrificing area.

Part 2 features advanced functionality that provide even more productivity and flexibility to the Laker SDL solution. It highlights powerful features for quickly duplicating repetitive layout pattern, including automatic dummy and guarding insertion, and pattern-based routing.

Mini Demo: EM/R Constraint Driven Editing and Analysis
EM/R constraint-driven editing and analysis helps automate the creation and editing of nets that must meet stringent EM/R requirements found in many of today’s high-speed SoCs. This capability is part of the IC Compiler Custom Co-Design solution that enables seamless full-custom editing between IC Compiler™ and Galaxy Custom Designer®.

Mini Demo: Advances in AMS Co-Design with IC Compiler
The seamless integration between IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development.

CustomExplorer Ultra: Mixed-signal Regression Management and Debug Environment
CustomExplorer Ultra is a comprehensive regression management and debug environment for mixed-signal SoC verification. Tightly integrated with Synopsys’ CustomSim simulator and CustomSim/VCS co-simulation solution, CustomExplorer Ultra aids engineers in rapidly performing customized advanced analyses for transistor-level analog, mixed-signal and SoC designs.

Mini Demo: Interactive Auto-Router
Custom Designer's Interactive Auto-Router is an innovative feature that improves single-net routing productivity. It comes in two modes of operation: Point-to-Point (P2P) and Follow-the-Cursor (FTC) routing. Both P2P and FTC will follow the preferred layer routing direction while routing nets LVS and DRC correct in real-time.

View All Custom Design News | View All Synopsys News
9/21/2016Synopsys and TSMC Collaborate to Certify Custom Compiler for 16FFC Process
TSMC Certified Synopsys Custom, Digital and Signoff Tools for 16FFC Process

5/19/2016Synopsys’ Custom Compiler Enabled for Samsung Foundry’s 14-nm FinFET Process
Samsung and Synopsys Collaborate to Deliver Custom Compiler-ready iPDK

5/2/2016Dongbu HiTek Provides Process Design Kits for Synopsys' Custom Compiler Solution
New iPDKs Streamline Development of Analog/Power and Mixed-signal Designs for High-growth Markets

3/30/2016Custom Compiler Pioneers New Era of Visually-assisted Automation
Shortens FinFET Custom Design Tasks from Days to Hours

3/30/2016Synopsys’ Custom Compiler Certified for TSMC 10-nm and 7-nm FinFET Process Nodes
TSMC and Synopsys Collaborate to Provide Custom Compiler-ready iPDKs

3/30/2016Synopsys’ Custom Compiler Deployed at STMicroelectronics to Boost IP Development Productivity
Template Assistants Shorten Layout Tasks


"We are focused on growing our business and contributing to establishing the Philippines as a center of semiconductor excellence. Custom Designer's ease of use, productivity and interoperability have allowed us to meet the needs of our diverse international customer base."

Jerome Avondo
CEO and President

"DRC correction in custom layout is a difficult and time-consuming activity, and we often have to go through multiple iterations to fix all errors. Bringing automation to this task will help increase engineering productivity and eliminate a tedious step in getting the layout finalized."

Ebi Abedifard
Vice President of Engineering
Avalanche Technology

"A single platform for both custom and cell-based design gives us the productivity gains we need to implement our complex mixed-signal designs more quickly. Custom Designer's tight integration within the Galaxy Implementation Platform provided us with a streamlined design flow, allowing us to focus more on our design and less on tool integration issues."

Dr. Lutz Porombka
Managing Director
Creative Chips, Inc.

"Smart phone customers demand the highest-quality images, so it is critical that we deliver camera modules early enough to be built into the next generation of phones. Synopsys' Custom Designer, coupled with expert field support, provides the most productive and complete custom implementation solution needed to meet our customers' requirements on schedule."

Roland Pudelko
Chief Executive Officer

"To support our custom memory IP business, we needed a complete, integrated custom IC design tool suite that could be rapidly adopted and deployed. The unified custom IC design solution from Synopsys, including Custom Designer, provides the productivity and performance our engineers need to quickly design and tape out IP at the 28-nanometer node."

Patrick Soheili
Vice President of Marketing and Business Development and General Manager of IP Solutions

"We switched to Synopsys’ custom solution because it offered greater productivity for our large, complex designs compared to our previous solution. We also found that Custom Designer’s open, standards-based environment made migration straightforward, with no impact to our design schedules. This was an important factor in our decision to adopt Synopsys."

Andrew Cole
General Manager and Vice President of Engineering

Synopsys collaborates with leading EDA vendors to provide advanced flows and methodologies for analog and custom design. The combination of Synopsys' technology leadership position in semiconductor design software and its ecosystem of partners gives Synopsys a unique ability to help address our customers' design challenges.

SAE Webinar
Improving Analog Verification Productivity Using Synopsys Simulation and Analysis Environment
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Custom Insight Blog
Join the discussion on moving custom layout into the 21st century by looking to the past for inspiration and the future for innovation.
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Verifying Signal and Power Integrity for Robust Design
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Latest News
Synopsys Redefines Circuit Simulation with Native Environment, Eliminating Need for Third-party Environment and Accelerating Analog Verification
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