A Unified Solution for Cell-based and Custom Design|
Synopsys provides a unified solution for cell-based and custom designs,
thereby enhancing SoC design efficiency and productivity. It is the first
custom implementation solution built on an open architecture supporting
interoperable process design kits (iPDKs) from leading foundries. Synopsys’
custom design solution delivers unmatched productivity with a common use
model for simulation, analysis, parasitic extraction and physical
Click on the diagram to access more information on
Synopsys' custom design tool suite.
|View All Webinars By Date | View All Webinar Categories|
|Advanced-node Custom Layout Using the Laker Custom IC Solution|
Learn about Laker’s rule-based layout, schematic-driven layout, and pattern-based multi-device layout features--ideal solutions for those seeking to improve custom layout productivity at 20-nm and below.
Neel Gopalin, Corporate Applications Engineer, Synopsys; Christopher Shaw, Senior Staff Technical Marketing Manager, Synopsys
|Accelerate Time-to-Tapeout with IC Compiler Custom Co-Design|
Learn how using IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development.
Christopher Shaw, Senior Staff Technical Marketing Manager, Synopsys; Randy Bishop, Principal Engineer, Synopsys
|Memory Timing Analysis and Characterization using NanoTime|
This webinar will outline the advanced features in NanoTime that enable designers to accurately and quickly identify timing issues associated with the embedded SRAM. Complex clocking analysis and mode.
Larry Jones, Synopsys Scientist, Implementation Group, Synopsys; Chad Lawrence, Staff Engineer, CAE, Implementation Group, Synopsys
|High-Productivity Analog Verification and Debug with CustomSim and CustomExplorer Ultra|
See how Synopsys' advanced analog verification solution can dramatically increase your verification productivity with CustomExplorer Ultra, along with CustomSim and CustomSim-VCS.
Duncan McDonald, Product Marketing Manager, Synopsys
|Get the Most from Your HSPICE Simulation|
Unleash the power of HSPICE simulations with useful tips and tricks to reduce simulation time without compromising HSPICE’s gold-standard accuracy.
Szekit Chan, HSPICE Staff Corporate Applications Engineer, Synopsys
|Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks|
Learn how process technology & changing design styles increase the impact of EM & IR-drop effects on the performance/reliability of AMS, memory & custom digital IP blocks at 28nm and below.
Bradley Geden, Solution Architect, Synopsys
|View All White Papers|
|Accelerated Layout for Analog/Mixed-Signal in Nanometer SoCs|
A much more accelerated approach for creating and integrating analog/mixed-signal functions in SoC designs is possible using automated methods to reduce the total effort needed, enable layout to proceed concurrently with circuit design, and typically produce more optimal layouts—especially for smaller die sizes.
Lyndon Lim, Synopsys
|Custom and Mixed-Signal Design Solution|
Synopsys’ unified solution for custom and cell-based design and verification provides a comprehensive, highly integrated suite of tools for advanced-node mixed-signal SoC design. The high degree of integration and interoperability shortens time-to-tapeout and improves design quality.
|Understand and Avoid Electromigration (EM) & IR-drop in Custom IP Blocks|
This whitepaper discusses the various trends exacerbating EM and IR-drop effects as well as design and analysis techniques to avoid them, and introduce Synopsys’ transistor-level analysis solution, which includes CustomSim for FastSPICE circuit simulation, StarRC for extraction, and Galaxy Custom Designer for custom layout.
Bradley Geden, Solutions Architect, Synopsys
|Unified Implementation Solution for Digital and Custom SoC Designs|
The Galaxy Implementation Platform provides seamless integration between the IC Compiler physical implementation
and Galaxy Custom Designer custom implementation solutions, accelerating the design development cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development while maintaining design data integrity.
|Automated Regression for Mixed-Signal Verification|
CustomExplorer™ Ultra represents the next generation in mixed-signal verification environment, including regression management, debug and analysis for complex SoC design.
Duncan McDonald, Product Marketing Manager, Synopsys
|SmartDRD Automated DRC Visualization and Correction|
SmartDRD is a new, innovative technology built into Galaxy Custom Designer™ Layout Editor (LE) for interactive DRC violation visualization, detection and correction, commonly known as design-rule-driven (DRD) editing
Mini Demo: EM/R Constraint Driven Editing and Analysis
EM/R constraint-driven editing and analysis helps automate the creation and editing of nets that must meet stringent EM/R requirements found in many of today’s high-speed SoCs. This capability is part of the IC Compiler Custom Co-Design solution that enables seamless full-custom editing between IC Compiler™ and Galaxy Custom Designer®.
CustomExplorer Ultra: Mixed-signal Regression Management and Debug Environment
CustomExplorer Ultra is a comprehensive regression management and debug environment for mixed-signal SoC verification. Tightly integrated with Synopsys’ CustomSim simulator and CustomSim/VCS co-simulation solution, CustomExplorer Ultra aids engineers in rapidly performing customized advanced analyses for transistor-level analog, mixed-signal and SoC designs.
Mini Demo: Interactive Auto-Router
Custom Designer's Interactive Auto-Router is an innovative feature that improves single-net routing productivity. It comes in two modes of operation: Point-to-Point (P2P) and Follow-the-Cursor (FTC) routing. Both P2P and FTC will follow the preferred layer routing direction while routing nets LVS and DRC correct in real-time.
Mini Demo: Layout Commands – Part Two
Automated Via Generation helps layout designers accelerate the tedious and repetitive tasks of wire connecting, substrate contact insertion, and power and ground tapping. This mini demo illustrates 5 different modes of operation from Custom Designer’s Auto-Via command.
Mini Demo: Layout Commands - Part One
SmartDRD DRDAssist enables layout designers to perform DRC-correct layout tasks at zoomed-out “high altitude", greatly reducing the number of zooming-in and zooming-out iterations. DRDAssist ensures DRC correctness by keeping objects separated at the minimum design rule distance, in real time.
Shadow Mode is a unique mechanism that highlights nets in their respective colors while dimming the background.
Smart Connect is an auto-connect feature for high-altitude wiring hookups, reducing the need to zoom in/out to ensure a correct connection that is clean, DRC- and LVS-correct.
"We are focused on growing our
business and contributing to establishing the Philippines as a
center of semiconductor excellence. Custom Designer's ease of
use, productivity and interoperability have allowed us to meet
the needs of our diverse international customer base."
Jerome Avondo |
CEO and President
"DRC correction in custom layout is a difficult and time-consuming
activity, and we often have to go through multiple iterations to
fix all errors. Bringing automation to this task will help
increase engineering productivity and eliminate a tedious step
in getting the layout finalized."
Vice President of Engineering
"A single platform for both custom and cell-based design gives us the
productivity gains we need to implement our complex mixed-signal
designs more quickly. Custom Designer's tight integration within
the Galaxy Implementation Platform provided us with a
streamlined design flow, allowing us to focus more on our design
and less on tool integration issues."
Dr. Lutz Porombka |
Creative Chips, Inc.
"Smart phone customers demand the highest-quality images, so it is
critical that we deliver camera modules early enough to be built
into the next generation of phones. Synopsys' Custom Designer,
coupled with expert field support, provides the most productive
and complete custom implementation solution needed to meet our
customers' requirements on schedule."
Roland Pudelko |
Chief Executive Officer
"To support our custom memory IP business, we needed a complete, integrated custom IC design tool suite that could be rapidly adopted and deployed. The unified custom IC design solution from Synopsys, including Custom Designer, provides the productivity and performance our engineers need to quickly design and tape out IP at the 28-nanometer node."
Patrick Soheili |
Vice President of Marketing and Business Development and General Manager of IP Solutions
"We switched to Synopsys’ custom solution because it offered greater
productivity for our large, complex designs compared to our
previous solution. We also found that Custom Designer’s open,
standards-based environment made migration straightforward, with
no impact to our design schedules. This was an important factor
in our decision to adopt Synopsys."
General Manager and Vice
President of Engineering
Synopsys collaborates with leading EDA vendors to provide advanced flows
and methodologies for analog and custom design. The combination of Synopsys'
technology leadership position in semiconductor design software and its
ecosystem of partners gives Synopsys a unique ability to help address our
customers' design challenges.
DAC Custom Design Lunch
Addressing Custom Design Challenges with Laker Reserve Your Seat
DAC AMS Luncheon
Advance Your Mixed-signal Verification Techniques to the Next Level Reserve Your Seat
Advanced-node Custom Layout Using the Laker Custom IC Solution Register Now
Mixed-Signal Verification—An ST-Ericsson Case Study Register Now