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A Unified Solution for Cell-based and Custom Design
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Synopsys provides a unified solution for cell-based and custom designs,
thereby enhancing SoC design efficiency and productivity. It is the first
custom implementation solution built on an open architecture supporting
interoperable process design kits (iPDKs) from leading foundries. Synopsys’
custom design solution delivers unmatched productivity with a common use
model for simulation, analysis, parasitic extraction and physical
verification.
Click on the diagram to access more information on
Synopsys' custom design tool suite. |
View All Webinars By Date | View All Webinar Categories
| | Get the Most from Your HSPICE Simulation | Unleash the power of HSPICE simulations with useful tips and tricks to reduce simulation time without compromising HSPICE’s gold-standard accuracy.
Szekit Chan, HSPICE Staff Corporate Applications Engineer, Synopsys |
| | Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks | Learn how process technology & changing design styles increase the impact of EM & IR-drop effects on the performance/reliability of AMS, memory & custom digital IP blocks at 28nm and below.
Bradley Geden, Solution Architect, Synopsys |
| | Use IC Compiler and Custom Designer to Shave Weeks Off Your SoC Development Cycle | Learn how the seamless integration between IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits at any stage of development.
Chris Shaw, Sr. Technical Marketing Manager, Synopsys;
Denis Goinard, CAE Manager, Synopsys |
| | Advanced Regression and Analysis for Mixed-Signal Verification Using CustomExplorer Ultra | Learn how CustomExplorer Ultra enables high verification productivity for complex SoCs using advanced strategies that surpass traditional verification approaches.
Duncan McDonald, Product Marketing Manager, Synopsys; Dwayne Holst, Corporate Applications Engineer, Synopsys
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| | Accurate Jitter and Noise Analysis Using HSPICE Transient Noise Techniques | Learn about new time-domain noise analysis approaches available in HSPICE, and how transient noise analysis can verify critical timing and noise performance characteristics.
Scott Wedge, Sr. Staff Engineer, Synopsys
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| | Advances in Circuit Analysis with the Custom Designer Simulation and Analysis Environment | Learn how to efficiently use Custom Designer's SAE in conjunction with HSPICE and Custom WaveView to analyze a design across process and parameter variations.
Kristin Beggs, R&D Engineer, Synopsys |
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View All White Papers
|  Understand and Avoid Electromigration (EM) & IR-drop in Custom IP Blocks | This whitepaper discusses the various trends exacerbating EM and IR-drop effects as well as design and analysis techniques to avoid them, and introduce Synopsys’ transistor-level analysis solution, which includes CustomSim for FastSPICE circuit simulation, StarRC for extraction, and Galaxy Custom Designer for custom layout.
Bradley Geden, Solutions Architect, Synopsys |
| | Unified Implementation Solution for Digital and Custom SoC Designs | The Galaxy Implementation Platform provides seamless integration between the IC Compiler physical implementation
and Galaxy Custom Designer custom implementation solutions, accelerating the design development cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development while maintaining design data integrity.
Synopsys |
| | Automated Regression for Mixed-Signal Verification | CustomExplorer™ Ultra represents the next generation in mixed-signal verification environment, including regression management, debug and analysis for complex SoC design.
Duncan McDonald, Product Marketing Manager, Synopsys
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| | SmartDRD Automated DRC Visualization and Correction | SmartDRD is a new, innovative technology built into Galaxy Custom Designer™ Layout Editor (LE) for interactive DRC violation visualization, detection and correction, commonly known as design-rule-driven (DRD) editing
Synopsys |
| | IC Validator: Physical Verification for Analog Designs | Physical verification challenges of analog designs are different than the challenges of large digital designs. In addition to complex runset requirements, a tight interface to a parasitic extraction tool and an easy-to-use GUI are needed to use a runset effectively in an analog design environment. IC Validator, the latest generation physical verification tool, can be used to solve these issues. This paper addresses many of the physical verification requirements of analog designers and how they are met with IC Validator.
Al Blais, Global Technology Services |
| | Accelerating Analog Simulation with HSPICE Precision Parallel Technology | HSPICE Precision Parallel technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SERDES, and other full mixed-signal circuits. HPP addresses the traditional bottleneck in accelerating SPICE on multicore CPUs with new algorithms that enable a larger percentage of the simulation to be parallelized, with no compromise in golden HSPICE accuracy. Additionally, efficient memory management allows simulation of
post-layout circuits larger than 10 million elements.
Robert Daniels, Sr. Staff Engineer, Synopsys Inc.; Harald Von Sosen, Principal Engineer, Synopsys Inc.; Hany Elhak, Product Marketing Manager, Synopsys Inc.
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CustomExplorer Ultra: Mixed-signal Regression Management and Debug Environment
CustomExplorer Ultra is a comprehensive regression management and debug environment for mixed-signal SoC verification. Tightly integrated with Synopsys’ CustomSim simulator and CustomSim/VCS co-simulation solution, CustomExplorer Ultra aids engineers in rapidly performing customized advanced analyses for transistor-level analog, mixed-signal and SoC designs.
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Mini Demo: Interactive Auto-Router
Custom Designer's Interactive Auto-Router is an innovative feature that improves single-net routing productivity. It comes in two modes of operation: Point-to-Point (P2P) and Follow-the-Cursor (FTC) routing. Both P2P and FTC will follow the preferred layer routing direction while routing nets LVS and DRC correct in real-time.
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Mini Demo: Layout Commands – Part Two
Automated Via Generation helps layout designers accelerate the tedious and repetitive tasks of wire connecting, substrate contact insertion, and power and ground tapping. This mini demo illustrates 5 different modes of operation from Custom Designer’s Auto-Via command.
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Mini Demo: Layout Commands - Part One
SmartDRD DRDAssist enables layout designers to perform DRC-correct layout tasks at zoomed-out “high altitude", greatly reducing the number of zooming-in and zooming-out iterations. DRDAssist ensures DRC correctness by keeping objects separated at the minimum design rule distance, in real time.
Shadow Mode is a unique mechanism that highlights nets in their respective colors while dimming the background.
Smart Connect is an auto-connect feature for high-altitude wiring hookups, reducing the need to zoom in/out to ensure a correct connection that is clean, DRC- and LVS-correct.
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"We are focused on growing our
business and contributing to establishing the Philippines as a
center of semiconductor excellence. Custom Designer's ease of
use, productivity and interoperability have allowed us to meet
the needs of our diverse international customer base." |
Jerome Avondo
CEO and President
APAC IC
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"DRC correction in custom layout is a difficult and time-consuming
activity, and we often have to go through multiple iterations to
fix all errors. Bringing automation to this task will help
increase engineering productivity and eliminate a tedious step
in getting the layout finalized." | Ebi
Abedifard
Vice President of Engineering
Avalanche Technology
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"A single platform for both custom and cell-based design gives us the
productivity gains we need to implement our complex mixed-signal
designs more quickly. Custom Designer's tight integration within
the Galaxy Implementation Platform provided us with a
streamlined design flow, allowing us to focus more on our design
and less on tool integration issues." |
Dr. Lutz Porombka
Managing Director
Creative Chips, Inc.
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"Smart phone customers demand the highest-quality images, so it is
critical that we deliver camera modules early enough to be built
into the next generation of phones. Synopsys' Custom Designer,
coupled with expert field support, provides the most productive
and complete custom implementation solution needed to meet our
customers' requirements on schedule." |
Roland Pudelko
Chief Executive Officer
DIS
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"We switched to Synopsys’ custom solution because it offered greater
productivity for our large, complex designs compared to our
previous solution. We also found that Custom Designer’s open,
standards-based environment made migration straightforward, with
no impact to our design schedules. This was an important factor
in our decision to adopt Synopsys." |
Andrew Cole
General Manager and Vice
President of Engineering
Foveon
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"The introduction of Custom Designer as part of the Galaxy Design
Platform provides a complete cell-based and custom design
capability that we are currently deploying on our
next-generation HDRC® sensor array design. Custom Designer was
easy to adopt, and offers significant productivity improvements
over other solutions." | Wolfram Klingler
Senior Manager, IC Design Tools
IMS
Chips
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Synopsys collaborates with leading EDA vendors to provide advanced flows
and methodologies for analog and custom design. The combination of Synopsys'
technology leadership position in semiconductor design software and its
ecosystem of partners gives Synopsys a unique ability to help address our
customers' design challenges.
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Latest NewsSynopsys Collaborates with Sigrity to Accelerate Signal Integrity Analysis
Read more | IC Compiler + Custom Designer WebinarShave Weeks Off Your SoC Development Cycle using IC Compiler and Custom Designer
Register Now | HSPICE Tips & TricksReduce simulation time without compromising HSPICE gold-standard accuracy Register now | HSPICE SIG 2012Attend the HSPICE SIG during DesignCon and hear what industry leaders say about using HSPICE in today’s designs
Register now |
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