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A Unified Solution for Cell-based and Custom Design

Synopsys provides a unified solution for cell-based and custom designs, thereby enhancing SoC design efficiency and productivity. It is the first custom implementation solution built on an open architecture supporting interoperable process design kits (iPDKs) from leading foundries. Synopsys’ custom design solution delivers unmatched productivity with a common use model for simulation, analysis, parasitic extraction and physical verification.

Click on the diagram to access more information on Synopsys' custom design tool suite.
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FineSim Technology for Analog and Full-Chip Simulation - A Micron Case Study
Learn about FineSim’s transient analysis advantage and the rich feature set that that combines SPICE and FastSPICE simulation technology in one single environment used for memory design at Micron.
Raed Sabbah, Sr. Design Engineer, Embedded Solutions Group, Micron Technology

Eliminate DDR3 Timing Errors with HSPICE and Zuken Constraint-based PCB Routing
Learn how to analyze signal integrity of critical traces in your PC board layout, incorporate board parasitics and define design constraints to eliminate timing violations.
Griff Derryberry, Applications Engineer, Zuken USA; Hany Elhak, Product Marketing Manager, Synopsys

Power Management ICs – Efficient Design: A Richtek and Synopsys Perspective
Richtek and Synopsys present the key challenges and trends with latest power management Integrated Circuits and discuss recent EDA tool innovations to shorten development time and maximize QoR.
K C Chang, Vice President, Technology Development, Richtek Technology Company; Andy Biddle, Solution Marketing Manager, Synopsys

Advanced-node Custom Layout Using the Laker Custom IC Solution
Learn about Laker’s rule-based layout, schematic-driven layout, and pattern-based multi-device layout features--ideal solutions for those seeking to improve custom layout productivity at 20-nm and below.
Neel Gopalin, Corporate Applications Engineer, Synopsys; Christopher Shaw, Senior Staff Technical Marketing Manager, Synopsys

Accelerate Time-to-Tapeout with IC Compiler Custom Co-Design
Learn how using IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development.
Christopher Shaw, Senior Staff Technical Marketing Manager, Synopsys; Randy Bishop, Principal Engineer, Synopsys

High-Productivity Analog Verification and Debug with CustomSim and CustomExplorer Ultra
See how Synopsys' advanced analog verification solution can dramatically increase your verification productivity with CustomExplorer Ultra, along with CustomSim and CustomSim-VCS.
Duncan McDonald, Product Marketing Manager, Synopsys

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Accelerated Layout for Analog/Mixed-Signal in Nanometer SoCs
A much more accelerated approach for creating and integrating analog/mixed-signal functions in SoC designs is possible using automated methods to reduce the total effort needed, enable layout to proceed concurrently with circuit design, and typically produce more optimal layouts—especially for smaller die sizes.
Lyndon Lim, Synopsys

Custom and Mixed-Signal Design Solution
Synopsys’ unified solution for custom and cell-based design and verification provides a comprehensive, highly integrated suite of tools for advanced-node mixed-signal SoC design. The high degree of integration and interoperability shortens time-to-tapeout and improves design quality.
Synopsys

Understand and Avoid Electromigration (EM) & IR-drop in Custom IP Blocks
This whitepaper discusses the various trends exacerbating EM and IR-drop effects as well as design and analysis techniques to avoid them, and introduce Synopsys’ transistor-level analysis solution, which includes CustomSim for FastSPICE circuit simulation, StarRC for extraction, and Galaxy Custom Designer for custom layout.
Bradley Geden, Solutions Architect, Synopsys

Unified Implementation Solution for Digital and Custom SoC Designs
The Galaxy Implementation Platform provides seamless integration between the IC Compiler physical implementation and Galaxy Custom Designer custom implementation solutions, accelerating the design development cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development while maintaining design data integrity.
Synopsys

Automated Regression for Mixed-Signal Verification
CustomExplorer™ Ultra represents the next generation in mixed-signal verification environment, including regression management, debug and analysis for complex SoC design.
Duncan McDonald, Product Marketing Manager, Synopsys

SmartDRD Automated DRC Visualization and Correction
SmartDRD is a new, innovative technology built into Galaxy Custom Designer™ Layout Editor (LE) for interactive DRC violation visualization, detection and correction, commonly known as design-rule-driven (DRD) editing
Synopsys

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Mini Demo: Laker Schematic-Driven Layout — Part 1
SDL methodology brings many benefits, but adoption has lagged because of the restrictions it sometimes places on layout flexibility. Laker’s next-generation SDL methodology is much more flexible, providing Laker users with the productivity benefits of SDL without sacrificing area.

Part 1 shows an intuitive schematic-driven layout solution that enables layout designers to optimize layout density through flexible, hierarchical device-level manipulation. Unlike competing tools, Laker does not require the layout and schematic hierarchies to match.


Mini Demo: Laker Schematic-Driven Layout — Part 2
SDL methodology brings many benefits, but adoption has lagged because of the restrictions it sometimes places on layout flexibility. Laker’s next-generation SDL methodology is much more flexible, providing Laker users with the productivity benefits of SDL without sacrificing area.

Part 2 features advanced functionality that provide even more productivity and flexibility to the Laker SDL solution. It highlights powerful features for quickly duplicating repetitive layout pattern, including automatic dummy and guarding insertion, and pattern-based routing.


Mini Demo: EM/R Constraint Driven Editing and Analysis
EM/R constraint-driven editing and analysis helps automate the creation and editing of nets that must meet stringent EM/R requirements found in many of today’s high-speed SoCs. This capability is part of the IC Compiler Custom Co-Design solution that enables seamless full-custom editing between IC Compiler™ and Galaxy Custom Designer®.


Mini Demo: Advances in AMS Co-Design with IC Compiler
The seamless integration between IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development.


CustomExplorer Ultra: Mixed-signal Regression Management and Debug Environment
CustomExplorer Ultra is a comprehensive regression management and debug environment for mixed-signal SoC verification. Tightly integrated with Synopsys’ CustomSim simulator and CustomSim/VCS co-simulation solution, CustomExplorer Ultra aids engineers in rapidly performing customized advanced analyses for transistor-level analog, mixed-signal and SoC designs.


Mini Demo: Interactive Auto-Router
Custom Designer's Interactive Auto-Router is an innovative feature that improves single-net routing productivity. It comes in two modes of operation: Point-to-Point (P2P) and Follow-the-Cursor (FTC) routing. Both P2P and FTC will follow the preferred layer routing direction while routing nets LVS and DRC correct in real-time.


View All Custom Design News | View All Synopsys News
6/3/2014Synopsys and Intel Collaborate to Enable 14-nm Tri-Gate Design Platform for Use by Customers of Intel Custom Foundry
Extends Production-Proven 22-nm Design Enablement to 14-nm for Cloud Infrastructure and Mobile Market Segments

4/14/2014TSMC Certifies Synopsys Digital and Custom Solution for V1.0 N16 Process
Certification Enables Designers to Realize the Power, Performance and Area Benefits of FinFET Technology

3/24/2014Synopsys Unveils IC Compiler II, Enabling a Game-Changing, 10X Increase in Physical Design Throughput


10/14/2013Synopsys and TSMC Collaborate to Deliver 16-nm Custom Design Reference Flow
TSMC Certifies Analog/Mixed-Signal Products for 16-nm Design Requirements

9/8/2013TSMC and Synopsys Extend Custom Design Collaboration into 16-nm
TSMC Certifies Laker Custom Design Solution for 16-nm FinFET and Provides iPDK

3/25/2013Synopsys Introduces Galaxy Custom Router
New Shape-Based Router Brings Automatic Custom Net Routing to IC Compiler Users

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"We are focused on growing our business and contributing to establishing the Philippines as a center of semiconductor excellence. Custom Designer's ease of use, productivity and interoperability have allowed us to meet the needs of our diverse international customer base."

Jerome Avondo
CEO and President
APAC IC

"DRC correction in custom layout is a difficult and time-consuming activity, and we often have to go through multiple iterations to fix all errors. Bringing automation to this task will help increase engineering productivity and eliminate a tedious step in getting the layout finalized."

Ebi Abedifard
Vice President of Engineering
Avalanche Technology

"A single platform for both custom and cell-based design gives us the productivity gains we need to implement our complex mixed-signal designs more quickly. Custom Designer's tight integration within the Galaxy Implementation Platform provided us with a streamlined design flow, allowing us to focus more on our design and less on tool integration issues."

Dr. Lutz Porombka
Managing Director
Creative Chips, Inc.

"Smart phone customers demand the highest-quality images, so it is critical that we deliver camera modules early enough to be built into the next generation of phones. Synopsys' Custom Designer, coupled with expert field support, provides the most productive and complete custom implementation solution needed to meet our customers' requirements on schedule."

Roland Pudelko
Chief Executive Officer
DIS

"To support our custom memory IP business, we needed a complete, integrated custom IC design tool suite that could be rapidly adopted and deployed. The unified custom IC design solution from Synopsys, including Custom Designer, provides the productivity and performance our engineers need to quickly design and tape out IP at the 28-nanometer node."

Patrick Soheili
Vice President of Marketing and Business Development and General Manager of IP Solutions
eSilicon

"We switched to Synopsys’ custom solution because it offered greater productivity for our large, complex designs compared to our previous solution. We also found that Custom Designer’s open, standards-based environment made migration straightforward, with no impact to our design schedules. This was an important factor in our decision to adopt Synopsys."

Andrew Cole
General Manager and Vice President of Engineering
Foveon

Synopsys collaborates with leading EDA vendors to provide advanced flows and methodologies for analog and custom design. The combination of Synopsys' technology leadership position in semiconductor design software and its ecosystem of partners gives Synopsys a unique ability to help address our customers' design challenges.

DAC Custom Lunch
Innovations in Custom Design
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DAC Circuit Simulation Luncheon
Complex Mixed-Signal SoCs: How to Conquer the Next Verification Frontier
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Latest News
TSMC Certifies Synopsys Digital and Custom Solution for V1.0 N16 Process
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FineSim Technology for Analog and Full-Chip Simulation - A Micron Case Study
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