HELPING YOU DESIGN THE CHIP INSIDE Products and Solutions ---------- SOLUTIONS ---------- Eclypse Low Power Solution Galaxy Design Platform • Design for Low Power • Design for Test • Design for Yield • RTL Synthesis • Physical Implementation • Sign-Off • Liberty CCS • SDC • Milkyway Discovery Verification Platform • Analysis and Debug Tools • Low-Power Verification • System Analysis & Design • Smart RTL Verification • Functional Equivalence Checking • Mixed-Signal • Languages Intellectual Property (IP) • DesignWare Library • DesignWare Verification IP • DesignWare Cores • DesignWare Star IP • DesignWare Foundry Libraries • IP Reuse Tools Design for Manufacturing • Design-Yield Analysis • Mask Synthesis • Mask Data Preparation • Lithography Verification • TCAD • Manufacturing Yield Management Professional Services • Tool and Methodology Deployment • Pilot Design Environment • Flow Optimization • Implementation • Verification Consulting • Concept to Parts • Core Hardening ---------- PRODUCTS ---------- BSD Compiler: Test synthesis Cadabra: Cell creation Calibration Library CATS: Mask data preparation Circuit Explorer: Analysis & Optimization coreAssembler coreBuilder coreConsultant CosmosLE: Layout design environment CosmosScope: Waveform analysis CosmosSE: Schem. design environment DC Ultra: RTL synthesis Design Analyzer: RTL synthesis Design Compiler: RTL synthesis DesignWare: Design & verif. IP DesignWare Virtual Platforms DFT Compiler MAX DFT Compiler: Test synthesis DSSA Sentry Enterprise: Layout editor ESP: Transistor-level Equivalence Checking Formality: Funct. equiv. checking Hercules: Physical verification HSIM HSPICE: Accurate circuit simulation IC Compiler IC Workbench Innovator: SoC / system modeling JupiterXT: Design planning Leda: RTL checker Library Compiler: Library compilation Liberty NCX: CCS Characterization Magellan: RTL formal verification Memory Solution Milkyway: Design database MVRC MVSIM NanoChar: 90 nanometer & below characterization NanoSim: Fast circuit simulation NanoTime Odyssey Defect/Odyssey YMS Paramos Pilot Design Environment Pioneer-NTB: SystemVerilog testbench automation Power Compiler: Power optimization PrimePower: Power analysis PrimeRail PrimeTime PX PrimeTime: Static timing analysis PrimeTime SI: Signal integrity analysis PrimeYield Tool Suite Proteus OPC PSM-Create & PSM-Check Raphael Raphael NXT Recipe Manager and Editor (RME) Saber: Multi-tech. simulation Scirocco: VHDL simulation Seismos Sentaurus Device Sentaurus Lithography Sentaurus Process Sentaurus Structure Editor Sentaurus TFM Sentaurus Topography Sentaurus Workbench SiVL-LRC: Lithography verification SpiceCheck SpiceExplorer Star-RCXT: Full-chip RC extraction Star-RCXT VX Star-SimXT: Fast circuit simulation System Studio: DSP algorithm design Taurus-Medici Taurus-TSuprem4 TestChip Products TetraMAX: ATPG VCS: Comprehensive RTL Verification VCS MX: Mixed-HDL simulation Vera: Testbench automation WaveView Analyzer DESIGN IMPLEMENTATION VERIFICATION INTELLECTUAL PROPERTY DFM/TCAD DESIGN SERVICES 20 YEAR ANNIVERSARY CORPORATE BROCHURE NEWSROOM EVENTS PRESS KIT PUBLIC RELATIONS EXEC. PRESENTATIONS ADVERTISEMENTS SYNOPSYS PUBLICATONS INDUSTRY LINKS OFFICE LOCATIONS Nihon Synopsys (NSKK) Tokyo Head Office Nihon Synopsys Co., Ltd., Head Office Sumitomo Fudosan Oimachi Ekimae Building 1-28-1 Oi, Shinagawa-ku Tokyo, Japan 140-0014 Phone: 011.81.3.5746.1500 Fax: 011.81.3.5746.1550 Osaka Branch Office Nihon Synopsys Co., Ltd. Osaka Branch Office Pias Tower 13F 3-19-3 Toyosaki, Kita-ku Osaka-shi, Osaka Japan 531-0072 Phone: 011.81.6.6359.8139 Fax: 011.81.6.6359.8149 CONTACT US  | FEEDBACK  | LOCATIONS  |  PRIVACY POLICY  |  LEGAL

© 2008 Synopsys, Inc. All Rights Reserved.