Webinars 


Identifying and Resolving Low Power Issues Before Tapeout
This webinar highlights how to find low power issues during verification using Formality.
Bob Hatt, Staff Corporate Applications Engineer, Synopsys
Sep 29, 2015

Identifying and Resolving Low Power Issues Before Tapeout - Traditional Chinese
This webinar highlights how to find low power issues during verification using Formality. - Traditional Chinese
Richard Su, Staff AC, Synopsys
Sep 29, 2015

Implement ARM® Cortex®-A53 Multi-core Network Computing Reference Design on Samsung 14LPP Using Lynx
This presentation will take you through implementation of a 16 processor ARM Cortex-A53 based network computing reference design targeting Samsung’s 14LPP FinFET technology using Lynx Design System.
Chad Gamble, Lynx Design System Staff CAE, Synopsys
Sep 09, 2015

Learn How to Accelerate Verification Closure with PCIe Gen4 VIP
This webinar shows how to leverage protocol, methodology, verification and productivity features of Synopsys VC VIP and UVM source code test suites for accelerated verification closure of PCIe Gen4 based designs.
Paul Graykowski, Senior Manager, PCIe VIP, Synopsys
Aug 19, 2015

TSMC/Synopsys CustomSim Collaboration for 16nm FinFET Design Success
Join TSMC and Synopsys as we discuss N16FF+/early N10 certification collaboration activities and how CustomSim 2015.06 addresses the design needs of FinFET technology nodes.
Jacob Ou, Technical Manager, TSMC; Tom Hsieh, Corporate Application Engineering Manager, Synopsys
Aug 12, 2015

STMicroelectronics’ Experience: Synopsys Logic BIST for Automotive and Safety-Critical Designs
ICs targeted for safety-critical applications must be able to perform in-system self-test in compliance with functional safety standards such as ISO 26262. In this webinar, Synopsys highlights synthesis-based logic BIST that addresses the self-test requirements for safety-critical designs. Our guest speaker from STMicroelectronics presents results and details of Synopsys’ test solution successfully deployed on production designs.
Cinzia Bartolommei, Senior DFT Engineer, STMicroelectronics; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Jul 30, 2015

STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95%
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
Sebastien Marchal, Principal Engineer, STMicroelectronics; Stephan Mahnke, Staff Corporate Applications Engineer, Synopsys
Jul 29, 2015

STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95% - Traditional Chinese
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
James Chuang, Senior Technical Marketing Manager, Synopsys
Jul 29, 2015

STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95% - Simplified Chinese
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
James Chuang, Senior Technical Marketing Manager, Synopsys
Jul 29, 2015

DDR Hardening - A Repeatable Process to Predictive Closure
Learn from Synopsys Professional Services experts how to accelerate hardening of DDR interface IP in context of SoC design and performance requirements.
Vikas Sethi, Manager, Professional Services, Synopsys; Karan Jain, Design Consultant, Professional Services, Synopsys
Jul 28, 2015

Using Foundation IP in Low-Power 40nm IoT Designs
This webinar will provide details on how foundation IP - logic libraries and embedded memories - can help designers of IoT applications take advantage of the power benefits available in 40nm processes.
Kenneth Brock, Product Marketing Manager, Logic Libraries, Synopsys
Jul 21, 2015

Automotive Ethernet Moving to Time-Sensitive Environments
Learn about the required network connectivity for automotive applications like ADAS and the importance of integrating Ethernet IP that is certified to be ASIL B Ready for ISO 26262 functional safety.
John Swanson, Product Line Manager, Synopsys
Jul 14, 2015

Configure, Integrate & Prototype IP in Minutes
IP blocks alone can't address designers' growing SoC design & integration challenges. Learn how DesignWare IP Prototyping Kits ease IP configuration & integration and accelerate software development.
Hugo Neto, Technical Marketing Manager for IP Prototyping Kits , Synopsys
Jun 03, 2015

Addressing Verification Challenges of Evolving Ethernet Speeds from 25/40/50/100G and Beyond
We will outline in detail the verification challenges of current and future Ethernet speeds and explain how Accellera UVM Methodology, IEEE 1800-2012 System Verilog Functional Coverage, and SystemVerilog Ethernet Verification IP empowers design and verification teams with methodology, techniques and tools they need to achieve success.
Shenoy Mathew, Senior Corporate Applications Engineer, Verification Group, Synopsys
May 20, 2015

Fast IP Software Development & Integration with Virtual & FPGA-Based Prototyping
Learn how integrating an ARMv8-based virtual prototype, an FPGA-based prototype, pre-verified IP, and PHY daughter boards, can accelerate time-to-market.
Charu Khosla, Staff Customer Application Engineer, Synopsys
May 19, 2015

Improve Productivity And Schedule Predictability With Accurate And Timely Status Reports Using Lynx Design Systems
Learn how Lynx' Design Tracker, a new data reporting feature, enables easy access to relevant data to provide a significant boost to designer’s productivity and help effectively manage project schedules.
Chris Smith, Lynx Design System Staff CAE, Synopsys
May 13, 2015

Optimize DDR Memory Subsystem Efficiency With Synopsys Platform Architect
A mobile device SoC subsystem case study how Platform Architect enables efficient design, performance analysis and optimization of multicore SoC architectures.
Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys
May 05, 2015

Advantest and Synopsys: Taking Test Cost Reduction to the Next Level
In this webinar, we highlight two methodologies, multisite test and concurrent test, that minimize test application time and maximize throughput.
Dave Armstrong, Director of Business Development, Advantest; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Apr 30, 2015

Qualcomm Achieves Significantly Faster TAT with StarRC Ultra-scalable SMC Solution
Qualcomm and Synopsys will discuss the latest productivity features inside StarRC that enabled Qualcomm to achieve significant speedup in extraction and faster design closure.
Khusro Sajid, Sr. Staff Engineer, Qualcomm; Arindam Chatterjee, Manager, R&D, Synopsys;
Apr 28, 2015

ARM Perspective: Area Reduction on ARM Mali Cost-Efficient GPUs
In this joint webinar, ARM describes methodologies, design choices and results achieved by an area-centric reference implementation of the ARM Mali GPU using Design Compiler Graphical and IC Compiler.
Pierre-Alexandre Bou-Ach, Physical Design Lead, ARM; Priti Vijayvargiya, Director of RTL Synthesis Product Marketing, Synopsys
Apr 23, 2015

Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO – with Samsung case study
Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.
Synopsys
Apr 22, 2015

Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO - with Samsung case study (Traditional Chinese)
Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.
Synopsys
Apr 22, 2015

Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO – Samsung (Simplified Chinese)
Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.
Synopsys
Apr 22, 2015

Implementing Next-Generation Vision Capabilities to Enhance Your SoC Designs
Learn about the architecture of the new DesignWare Embedded Vision (EV) Processors and the open source vision tools used to program the processors to ensure efficient resource utilization.
Mike Thompson, Sr. Product Marketing Manager, Synopsys
Apr 21, 2015