Configure, Integrate & Prototype IP in Minutes
IP blocks alone can't address designers' growing SoC design & integration challenges. Learn how DesignWare IP Prototyping Kits ease IP configuration & integration and accelerate software development.
Hugo Neto, Technical Marketing Manager for IP Prototyping Kits , Synopsys
Jun 03, 2015

Addressing Verification Challenges of Evolving Ethernet Speeds from 25/40/50/100G and Beyond
We will outline in detail the verification challenges of current and future Ethernet speeds and explain how Accellera UVM Methodology, IEEE 1800-2012 System Verilog Functional Coverage, and SystemVerilog Ethernet Verification IP empowers design and verification teams with methodology, techniques and tools they need to achieve success.
Shenoy Mathew, Senior Corporate Applications Engineer, Verification Group, Synopsys
May 20, 2015

Fast IP Software Development & Integration with Virtual & FPGA-Based Prototyping
Learn how integrating an ARMv8-based virtual prototype, an FPGA-based prototype, pre-verified IP, and PHY daughter boards, can accelerate time-to-market.
Charu Khosla, Staff Customer Application Engineer, Synopsys
May 19, 2015

Improve Productivity And Schedule Predictability With Accurate And Timely Status Reports Using Lynx Design Systems
Learn how Lynx' Design Tracker, a new data reporting feature, enables easy access to relevant data to provide a significant boost to designer’s productivity and help effectively manage project schedules.
Chris Smith, Lynx Design System Staff CAE, Synopsys
May 13, 2015

Optimize DDR Memory Subsystem Efficiency With Synopsys Platform Architect
A mobile device SoC subsystem case study how Platform Architect enables efficient design, performance analysis and optimization of multicore SoC architectures.
Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys
May 05, 2015

Advantest and Synopsys: Taking Test Cost Reduction to the Next Level
In this webinar, we highlight two methodologies, multisite test and concurrent test, that minimize test application time and maximize throughput.
Dave Armstrong, Director of Business Development, Advantest; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Apr 30, 2015

Qualcomm Achieves Significantly Faster TAT with StarRC Ultra-scalable SMC Solution
Qualcomm and Synopsys will discuss the latest productivity features inside StarRC that enabled Qualcomm to achieve significant speedup in extraction and faster design closure.
Khusro Sajid, Sr. Staff Engineer, Qualcomm; Arindam Chatterjee, Manager, R&D, Synopsys;
Apr 28, 2015

ARM Perspective: Area Reduction on ARM Mali Cost-Efficient GPUs
In this joint webinar, ARM describes methodologies, design choices and results achieved by an area-centric reference implementation of the ARM Mali GPU using Design Compiler Graphical and IC Compiler.
Pierre-Alexandre Bou-Ach, Physical Design Lead, ARM; Priti Vijayvargiya, Director of RTL Synthesis Product Marketing, Synopsys
Apr 23, 2015

Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO – with Samsung case study
Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.
Apr 22, 2015

Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO - with Samsung case study (Traditional Chinese)
Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.
Apr 22, 2015

Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO – Samsung (Simplified Chinese)
Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.
Apr 22, 2015

Implementing Next-Generation Vision Capabilities to Enhance Your SoC Designs
Learn about the architecture of the new DesignWare Embedded Vision (EV) Processors and the open source vision tools used to program the processors to ensure efficient resource utilization.
Mike Thompson, Sr. Product Marketing Manager, Synopsys
Apr 21, 2015

Accelerate DesignWare IP Driver Development for ARMv8-based Designs with Virtualizer Development Kits
Understand how Virtualizer™ Development Kits (VDKs) can be used to accelerate DesignWare® Interface IP driver development and integration into a 64-bit ARMv8 Linux software stack.
Achim Nohl, Technical Marketing Manager, Synopsys
Apr 16, 2015

"Shift Left" Functional Safety for Automotive System Development
Since safety is one of the most challenging problems in the automotive industry, we will look at fault mode and effect analysis (FMEA) using virtual prototyping and physical modeling and simulation.
Nicolas Brown, Corporate Applications Engineer, Synopsys; Victor Reyes, Technical Marketing Manager, Synopsys
Apr 15, 2015

Picking up the pieces: self-contained verification platforms for the modular smartphone era
In the framework of Mobile platforms, learn how source code testsuites provided with Verification IP enable verification engineers to quickly generate diverse permutations of random/constrained random transactions that stress test the systems and subsystems, contributing to "Shift Left" of the verification time and ensure bug free designs.
Nitin Agrawal, CAE Manager, Verification Group, Synopsys
Apr 07, 2015

Choosing the Optimal Multiprotocol PHY IP for Your SoC
Learn about the architectural differences between enterprise and consumer multiprotocol PHY and the optimal PHY solution for your SoC that meets your specific design requirements.
Rita Horner, Sr. Technical and Product Marketing Manager, Synopsys
Apr 02, 2015

Meeting 90-nm to 10-nm Physical IP Design Requirements for Wearables and Application Processors
Understand the 90-nm to 10-nm technology process and IP requirements for wearable/IoT devices and mobile application processors.
Navraj Nandra, Sr. Director of Marketing for the DesignWare Analog/Mixed Signal IP, Synopsys
Mar 31, 2015

Design, Test & Repair Methodology for FinFET-based Memories
Understand the challenges associated with testing FinFET-based memories and new methods to address FinFET-specific defects.
Dr. Yervant Zorian, Chief Architect and Fellow, Synopsys
Mar 03, 2015

An Approach for Efficient IP Reuse in a Hierarchical UPF Methodology
This webinar will help you understand a Liberty-based approach for effective IP reuse in implementation of a multi-voltage hierarchical design using the IEEE 1801 (UPF) standard.
Viswanath K. Ramanathan, Corporate Applications Engineer, Synopsys; Mary Ann White, Director of Product Marketing, Synopsys
Feb 26, 2015

Designing SoCs for USB Type-C Products
Understand the USB Type-C specification from an SoC designer’s perspective, how to add USB Type-C to existing designs and recommendations for new SoC architectures.
Morten Christiansen, Technical Marketing Manager, Synopsys; Gervais Fong, Senior Product Manager, Synopsys
Feb 18, 2015

STMicroelectronics: Successful Last-minute Functional ECO Implementation with Formality Ultra
STMicroelectronics describes how they used Formality® Ultra to meet their tight release schedule for their ARM® core based designs despite having to implement multiple functional ECOs late.
Kailash Digari, Group Manager CPU-GPU design, STMicroelectronics; John Lehman, Senior CAE Manager, Synopsys
Feb 05, 2015

Successful GPU IP Implementation on Synopsys HAPS Platforms using ProtoCompiler
Learn how Synopsys ProtoCompiler and debug tool coupled with the flexible HAPS prototyping systems helps GPU developers tackle implementation of complex GPU IP and its end applications.
Andy Jolley, Senior Staff Application Consultant, Synopsys
Feb 04, 2015

Getting the Most out of IP-based Designs with Synplify FPGA Design Tools
Learn how to streamline and automate your IP-based FPGA design flow using Synopsys FPGA design tools, allowing you to attain your design objectives within the framework of how IP will be delivered.
Parminder Gill, Engineering Project Leader, FPGA Implementation, Synopsys
Feb 03, 2015

Automate Low Power Verification and Implementation Flow with VC Apps
UPF imported into Verdi's database provides valuable information to understand relationships between logic designs to power its intent. Learn how VC Apps APIs allows users to check if the design meets the requirements of low power design rules, and helps automate the implementation of low power design structure.
Rich Chang, Product Marketing Manager, Debug, Synopsys; Paul Huang, Corporate Application Engineer (CAE), Synopsys
Jan 28, 2015