Learn how to use Synopsys' synthesis-based test solution to reduce test cost and improve test quality for designs with few available test pins, and for designs with multiple power domains.
Robert Ruiz, Senior Product Marketing Manager, Synopsys; Carl Holzwarth Corporate Applications Engineering Director, Synopsys; and Brad MacMonagle Senior Staff Applications Consultant, Synopsys
May 23, 2012

Learn about GLOBALFOUNDRIES??? foundry-fabless collaboration model for volume diagnostics that resolves the issue of gaining access to closely guarded design data by eliminating the need for design IP to leave foundry customers.
Thomas Berndt, MTS Product Engineer, Yield Engineering, GLOBALFOUNDRIES Dresden
May 17, 2012

Learn how to efficiently explore and optimize the dynamic system performance of an Arteris FlexNoC based SoC design in SystemC using a mobile device case study example in Synopsys' Platform Architect.
Kurt Shuler, Vice President of Marketing, Arteris; Patrick Sheridan, Senior Staff Product Marketing, Synopsys; Tim Kogel, Solution Architect, Synopsys
May 15, 2012

Using the Lynx Design System, you will learn how to leverage the advanced timing closure features available with Synopsys’ IC Compiler and PrimeTime.
Aditya Ramachandran, Lynx CAE, Synopsys
May 09, 2012

Overview of challenges of verifying a coherent design. Shows how the features and architecture of Synopsys’ new Discovery VIP helps overcome these challenges to simplify verification of ACE design.
Abhijeet Khopkar, R&D Manager, Synopsys; Neill Mullinger, Group Marketing Manager, Synopsys
May 08, 2012

Learn how Formality utilizes powerful links with Design Compiler that enable you to achieve maximum Quality of Results (QoR) while maintaining verifiability.
Joe Bosia, Corporate Applications Engineer, Synopsys
May 03, 2012

TSMC and Synopsys will jointly present some of the key design and manufacturing challenges at 20nm process technology. They will highlight the need for early collaboration between EDA, customers and the foundry to ensure a smooth path to tape-out and first-time silicon success.
Willy Chen, Department Manager, Design Methodology & Service Marketing Program R&D, TSMC; Dr. Tong Gao, Synopsys Fellow, Synopsys
May 01, 2012

Learn how dedicated audio subsystems can offload the audio processing from the host processor, thus reducing design complexity and improving performance and efficiency of SoCs.
Henk Hamoen, Senior Product Marketing Manager, Synopsys
Apr 26, 2012

Learn how to achieve a 2X reduction in signoff TAT, and build the expertise to create high-performance signoff scripts.
Tzong-Maw Tsai, CAE Director, Synopsys; Amrita Sahoo, Senior Corporate Applications Engineer, Synopsys
Apr 25, 2012

Learn about the frequency domain mechanisms that relate jitter to sampling errors which enables designers to handle the design trade-offs and to achieve optimal system and data converter performance.
Carlos Azeredo-Leme, Senior Staff Engineer for the DesignWare Analog IP, Synopsys
Apr 24, 2012

In this webinar, you will be introduced to the Altera SoC FPGA for the Altera Cyclone V and Arria V SoC FPGA devices and its associated Virtual Target.
Stephen Lim, Product Marketing Manager, Altera; Marc Serughetti, Product Marketing Director, Synopsys
Apr 19, 2012

Learn how Synopsys aligns application/market needs to provide embedded multiple time programmable (MTP) non-volatile memory (NVM) IP at advanced nodes with optimized, targeted technology capabilities
Craig Zajac, Senior Product Marketing Manager, Synopsys
Apr 12, 2012

Hear Synopsys discuss the physical modeling of ESD structures, with a focus on the underlying physical mechanisms that limit protection, and illustrate the TCAD ESD design methodology in a 32nm bulk C
Chan-Su Yun, Senior Staff R&D Engineer, Synopsys; Sudarshan Krishnamoorthy, Technical Marketing Mgr, Synopsys
Apr 11, 2012

Synopsys and LSI jointly present on designing today’s high frequency, low power clocks. LSI will present their perspective on the challenges of clock distribution and Synopsys will focus on the solutions that enable designers to achieve the best QoR and lowest power at today’s advanced technology nodes.
JC Parker, Senior Director of Design Tools and Methodologies, LSI; Dennis Ding, R&D Director, Synopsys
Apr 04, 2012

Learn what’s new with timing-aware DRC guidance for ECOs and which design flow and tool settings provide the fastest timing closure at 28 nm and below.
Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys; Vivek Ghante, Staff Corporate Applications Engineer, Implementation Group, Synopsys
Mar 14, 2012

Learn about the LTE-Advanced standard (3GPP Rel.10), its main enhancements over LTE Rel.8 and their impact on the overall system performance.
Dr. Vafa Ghazi-Moghadam, Staff R&D Engineer, Synopsys Inc.
Mar 08, 2012

This webinar will show you the various steps to easily generate, view, refine and debug the power intent of your design, as specified with the IEEE 1801 (UPF) format. You will learn effective techniques to speed up the implementation of your advanced low power designs. This webinar will be valuable for both new and experienced users of power intent. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Sebastian Brugnoli, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Mar 07, 2012

Learn how custom processors or ASIP can provide the right trade-off between flexibility and power, performance and area requirements.
Drew Taussig, Corporate Applications Engineer, Synopsys
Feb 28, 2012

Learn about the ARC processor architecture in the DesignWare ARC Android solution which enables performance optimizations for the most power and cost sensitive market segments.
Chris Caerts, Product Marketing Manager, Synopsys, Inc.
Jan 18, 2012

In this seminar, we will demonstrate silicon-proven methodologies to describe power intent with IEEE 1801 (UPF) using a hierarchical design flow to address power consumption and design size concurrently. We will walk you through some of the key steps in implementing and analyzing a hierarchical design using UPF for both bottom-up and top-down Synopsys Galaxy-based flows.
Chad Gamble, Synopsys
Jan 17, 2012

See examples of how FPGA-based prototyping can be used to deal with the high data rates of multi-channel, wideband digital systems while reducing systems validation and hw/sw integration costs.
Neil Songcuan, Product Marketing Manager, Synopsys; Gary Goncher, Applications Engineer and System Architect, Tektronix
Jan 11, 2012

How Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications
Ting-Jia Hu, Sr. Program Manager for DesignWare NVM IP, Synopsys
Jan 10, 2012

Unleash the power of HSPICE simulations with useful tips and tricks to reduce simulation time without compromising HSPICE’s gold-standard accuracy.
Szekit Chan, HSPICE Staff Corporate Applications Engineer, Synopsys
Nov 30, 2011

Learn about the LTE-A standard (Rel.10) with a focus on the downlink configuration, and understand the main enhancements over LTE Rel.8 and their implication on the overall system complexity.
Vafa Ghazi-Moghadam, R&D Engineer, Synopsys
Nov 15, 2011