Webinars 


How Reliable is Your FPGA Design? Tips and Tricks for Building-in High Reliability
Learn how to automatically "build in" high reliability using Synopsys Synplify Premier FPGA design tool.
Sharath Duraiswami, Senior Corporate Applications Engineer, Synopsys
Oct 02, 2014

Increase Designer Productivity and Accelerate SoC Design Schedule Through Flow Automation
The complexities of advanced SoC design constantly challenge tape-out timelines. Synopsys' Lynx Design System can simplify and automate flows for many critical implementation and validation tasks, enabling engineers to focus on achieving performance goals. This webinar will introduce you to how customers such as Altera are leveraging Lynx in their design flows to lower risk and improve predictability. Additionally, you will learn about innovative and sophisticated automation solutions for design QoR analysis, correlation and regression that accelerate design schedules.
Lydia Lee, Lynx Design System Staff CAE, Synopsys
Sep 10, 2014

VCS AMS for Advanced SoC Mixed-signal Verification
Learn how ARM and STMicroelectronics are using the advanced verification techniques and productivity features of VCS AMS to verify their mixed-signal SoC designs.
Helene Thibieroz, VCS AMS Product Marketing Manager, Synopsys, Inc.; Pierluigi Daglio, AMS Design Verification Flows Manager, STMicroelectronics; Venkatesh Bharanthi Krishnamurthy, Manager of Design Automation, ARM
Sep 03, 2014

Moore's Cores - Best Practices to Optimize Processor Cores for Performance, Power and Area Targets Specific to Your SoC (in Mandarin)
As silicon capacity continues to grow following Moore's law, so has the growth in computational power. This, along with the complexities of today's designs, has led to the need for multi-processor core SoC's to achieve design goals. Managing the complexity of designs that include CPUs, GPUs, and DSPs in a single chip can be quite challenging. Based upon years of Synopsys' consulting experience implementing hundreds of these SoC's, this webinar will outline design best practices and pitfalls to avoid, to enable you to achieve the right balance of high performance, low power and smaller area.
HuaMin Hou, Senior Design Consultant, Synopsys
Aug 27, 2014

Creating a High-Performance TBE Environment
Transaction-based emulation or TBE has become an increasingly popular method for utilizing emulators because of the high verification performance and flexibility in connecting to existing environments.
Lance Tamura, CAE Manager, Verification Group, Synopsys
Aug 12, 2014

Advanced Mixed-Signal Design and Verification of Smartcar ICs
In this webinar, Micronas and Synopsys discuss the breadth of automotive IC applications, challenges in design implementation and verification and the solutions that stemmed from their collaboration.
Mario Anton, Micronas; Gernot Koch, Micronas; Marco Casale-Rossi, Synopsys
Jul 31, 2014

ProtoCompiler Accelerates HAPS FPGA-Based Prototyping Systems
This webcast examines the latest generation of design tools for prototyping, Synopsys ProtoCompiler, a suite of design automation and debugging tools for the Synopsys HAPS Series of FPGA-based prototypes.
Troy Scott, Product Marketing Manager, Synopsys
Jul 23, 2014

FinFETs For Your Next SoC: To Move or Not To Move?
Learn about the benefits and challenges of moving from a planar CMOS process to FinFET and how DesignWare embedded memory and logic library IP can enable this move.
Prasad Saggurti, Product Marketing Manager for Embedded Memory IP, Synopsys
Jul 22, 2014

Verifying Clock Domain Crossings in Complex SoCs – Are You Sure You Caught All the Bugs?
Avoid missing a CDC bug that causes a silicon re-spin! The Synopsys VC CDC solution provides comprehensive CDC verification at RTL for any size design, up to and including SoC full-chip flat, enabling designers to find and debug CDC issues early in the design cycle. We’ll discuss why our solution will find bugs that purely hierarchical solutions will miss, and do so with far less designer impact than any other solution.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Namit Gupta, Corporate Application Engineer (CAE), Verification, Synopsys; Kaushik De, Scientist at Synopsys, Design Verification, Synopsys
Jul 16, 2014

Designing with Non-Volatile Memory for High-Volume Automotive ICs
Learn about the challenges with designing high-volume automotive ICs and the associated non-volatile memory requirements for high performance, high reliability, and optimized area.
Angela Raucher, Product Line Manager, Synopsys; Martin Niset Senior R&D Manager, Synopsys
Jul 15, 2014

Imagination and Synopsys: Reduce Dynamic Power and Area up to 50% on a GHz+ MIPS Core Implementation
In this webinar, Imagination Technologies will share how their selection of standard cell architecture and use of several dynamic power techniques available in Design Compiler and IC Compiler helped them achieve optimal power and area savings for their MIPS family of CPU cores.
Maya Mohan, Hardware Design Engineer, Imagination Technologies and Jeffrey Lee, CAE Manager, Power Compiler, Synopsys
Jul 10, 2014

Achieving Ultra-Low DPPM: Avago Case Study
Hear experts from Avago and Synopsys describe key advanced fault models available in Synopsys' synthesis-based test solution, DFTMAX and TetraMAX ATPG, to achieve ultra-low DPPM.
Stefano Zanatta, DFT Engineer, Avago Technologies; Adam Cron, Principal Engineer, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Jun 26, 2014

Automate ASIC to FPGA-based Prototype Conversion with Synplify
Using Synplify, automate ASIC to FPGA-based prototype conversion to accelerate fast FPGA-based working prototype bring-up, debug and validation.
Dr. Angela Sutton, Staff Product Marketing Manager, FPGA Implementation, Synopsys
Jun 18, 2014

Advanced-Node Variability Characterization and STA Margining with SiliconSmart and PrimeTime
Learn about the new slew-/load-dependent POCV delay model, and hear GLOBALFOUNDRIES describe their experiences using SiliconSmart and PrimeTime to implement a variation-based methodology for advanced
Dr. Tamer Ragheb, SMTS Design CAD Engineer, GLOBALFOUNDRIES; Moninder Bansal, Senior Manager, Corporate Applications Engineering, Synopsys
Jun 11, 2014

How to Accelerate the Development of ARMv8 Based Server
Learn about tools and methods for early bring-up and debug of software stacks for ARMv8-based SoCs and servers.
Achim Nohl, Technical Marketing Manager, Synopsys; Marc Serughetti, Director of Business Development, Synopsys
Jun 10, 2014

Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow - Simplified Chinese
Simplified Chinese: Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Chung Yang, CAE, Synopsys
May 28, 2014

Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow - Traditional Chinese
Traditional Chinese: Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Chung Yang, CAE, Synopsys
May 28, 2014

Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow
Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Carol Scemanenco, Senior Staff Engineer, Synopsys
May 27, 2014

Extending Proven Digital Verification Techniques for Mixed-Signal SoCs with VCS AMS
VCS AMS provides mixed-signal verification with a unique performance advantage due to tight integration of VCS functional verification and CustomSim FastSPICE simulation. Webinar topics include an introduction of the new VCS AMS mixed-signal verification solution, RNM with VCS, the SystemVerilog-based AMS testbench methodology, low power verification using UPF power intent specification and AMS debug with Verdi.
Rebecca Lipon, Senior Product Marketing Manager, Verification Group, Synopsys; Arturo Salz, Synopsys Scientist, Verification Group, Synopsys
May 21, 2014

Performance Analysis and Optimization of ARM® CoreLink™ NIC-400 based Systems
A case study demonstration of system-level performance analysis and optimization.
William Orme, Strategic Marketing Manager, Interconnect products, ARM; Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys
May 20, 2014

Addressing the Challenges of Multi-Protocol High Speed PHY IP in SoC Design
This webinar describes the design challenges and potential advantages of using a multi-protocol 12.5 Gbps PHY that supports a wide range of data rates, features and specifications.
Rita Horner, Product Marketing Manager, Synopsys; Paul Hua, R&D Manager, Synopsys
May 15, 2014

Latest Advances in PrimeRail In-Design Vector Free Rail Analysis
See the latest innovations in PrimeRail's In-Design solution including rail integrity and static/dynamic analysis that enable designers to achieve significant productivity in advanced node designs.
Jason Binney, Principle CAE, Synopsys
May 14, 2014

Moore's Cores - Best Practices to Optimize Processor Cores for Performance, Power and Area Targets Specific to Your SoC
As silicon capacity continues to grow following Moore's law, so has the growth in computational power. This, along with the complexities of today's designs, has led to the need for multi-processor core SoC's to achieve design goals. Managing the complexity of designs that include CPUs, GPUs, and DSPs in a single chip can be quite challenging. Based upon years of Synopsys' consulting experience implementing hundreds of these SoC's, this webinar will outline design best practices and pitfalls to avoid, to enable you to achieve the right balance of high performance, low power and smaller area.
Jonathan Young, Director, Design Consulting, Synopsys
May 13, 2014

FineSim Technology for Analog and Full-Chip Simulation - A Micron Case Study
Learn about FineSim’s transient analysis advantage and the rich feature set that that combines SPICE and FastSPICE simulation technology in one single environment used for memory design at Micron.
Raed Sabbah, Sr. Design Engineer, Embedded Solutions Group, Micron Technology
May 08, 2014