Location Proceedings

Scan Compression Without "Scan Compression" (1st Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Richard Illman , Hans-Martin von Staudt [Dialog Semiconductor Ltd.]

Paper

Presentation

Webinar

B4 User Paper & Tutorial

Migrating to UVM: how and why!
Author(s): Mike Bartley [TVS]

Paper

Presentation

B5 User Paper & Tutorial

PLL characterization using HspiceRF in Custom Designer Environment
Author(s): Jan Sysr [CertiCon], Saad Jabir [Synopsys, GmbH.]

Paper

Presentation

C3 User Paper & Tutorials

My Equivalence Checking flow has been UPF-ed! Constraining Low Power States in Formality
Author(s): Neil Bray [ARM]

Paper

Presentation

C5 User Paper & Tutorial

Integrated Actuator Control for Mobile Camera Applications using Custom Designer Analog/Mixed-Signal Design Flow
Author(s): Frank Kronmueller [Digital Imaging Systems GmbH], Rudolph Walter [Synopsys GmbH.]

Paper

Presentation

Tutorials

A1 User Experience & Tutorial

Synplify Pro / Premier Technology Enhancements to Address Run-Time and Design Stability Issues
Author(s): Paul Rolfe [Broadcom. Corp.], Andy Jolley [Synopsys Ltd.]

Tutorial

User Experience

A3 Tutorial

You Have the Power to TEST! | Reducing the Cost of Pin-Limited Test Using DFTMAX Compression
Author(s): Dave Johnson [Synopsys Ltd.]

Tutorial

Webinar

A5 User Presentation & Tutorial

HSIMplus CircuitCheck for Low Power Transistor Level Error Detection
Author(s): Kevin Chen [Synopsys Inc.]

Tutorial

B1 User Experience & Tutorial

Getting the most from H/W Prototyping with the Confirma Rapid Prototyping Solutions
Author(s): Gavin Dolling [DisplayLink Ltd.], Frank McMillan [Synopsys Ltd.]

Tutorial

User Experience

B2 User Paper & Tutorial

PrimeRail and IC Compiler: In-Design Rail Analysis for Faster Power Network Design Closure
Author(s): Jon Dawes [Synopsys Ltd.]

Tutorial

B4 User Paper & Tutorial

What’s new in the SystemVerilog IEEE 1800 - 2009 LRM?
Author(s): Yassine Eben Aimine [Synopsys Ltd.]

B5 User Paper & Tutorial

Demonstration of Custom Designer
Author(s): Damian Roberts [Synopsys Ltd.]

C1 Tutorial

Effective FPGA Design Analysis and Debugging
Author(s): Andy Jolley [Synopsys Ltd.]

Tutorial

R&D Vision for Future FPGA Design Methodologies Web-Ex with Jim Robinson - VP Engineering - FPGA Synthesis
Author(s): Doug Amos [Synopsys Ltd.]

C2 Tutorial

Energy Efficient Processor Implementation with Synopsys’ Eclypse Low Power Solution
Author(s): Alan Gibbons [Synopsys Ltd.]

Tutorial

Webinar

Extreme Low-Power Datapath Design with DesignWare minPower Components
Author(s): Tom Ryan [Synopsys Ltd.]

Tutorial

C3 User Paper & Tutorials

Faster Timing Convergence with PrimeTime ECO
Author(s): Simon Bloyce [Synopsys, Ltd.]

Tutorial

Galaxy Constraint Analyzer: Constraint Debug Made Easy
Author(s): Simon Bloyce [Synopsys, Ltd.]

C4 Vision, User Experience & Tutorial

Achieving design closure and correlation using DC Graphical
Author(s): James Myers [ARM Ltd.], Laurens Drost [Synopsys, Ltd.]

Presentation

Tutorial

C5 User Paper & Tutorial

Efficient Analog IP Migration: A Migration Experience from Synopsys Analog IP
Author(s): Luis Matias [Synopsys Portugal]

Tutorial

SNUG UK 2010 Proceedings