SNUG Taiwan 2010 Proceedings

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Complete Proceedings


User Papers and Presentations
TA1-ICC/Lynx
Low power CTS technique using optimal ICG placement (Best Paper Award)
Author(s): 陳軍, Dhaval Bhatia,王孝誠, 張裕東 [Mediatek]
PaperPresentation

Multi-Media design put into use ICC ILM flow
Author(s): ShiZhi [Realtek]
Presentation

TA2-STA/Test/Lynx
3D IC Implementation
Author(s): 李鴻禧、陳振岸、陳繼展 [工業技術研究院]
Presentation

Boost PrimeTime Productivity Using Multicore
Author(s): Eason Lin [Via]
Presentation

Reduce Power Consumption in High Performance IP with Synopsys Designware minPower Solution
Author(s): Mexx Lin [Faraday]
Presentation

Scan Test Power Reduction Using Power-aware ATPG (Best Paper Award)
Author(s): Pei-Ying Hsueh, Shuo-Fen Kuo, Ying-Yen Chen, Jin-Nung Lee, Chi-Feng Wu [Realtek]
PaperPresentation

TA3-VMM
Adopting vmm_subenv in SOC projects
Author(s): Cheng Chung Yuan, An Hsiao Cheng [Realtek]
PaperPresentation

Methodology of Executable Verification Plan (Technical Committee Award Honorable Mention)
Author(s): Shang-Wei Tu [Sunplus]
PaperPresentation

TB3-VMM/ESL
ESL Virtual Platform for System Performance Enhancement (Best Paper Award)
Author(s): Jen-Chieh Yeh [ITRI]
Presentation

Using VMM to Address DTV Transport Processor Verification Challenges
Author(s): Temin Kuo [Realtek]
PaperPresentation

WA1 - ICC
N40 DFM Implementation Flow
Author(s): Ken Wang [TSMC]

Reference Flow
Author(s): 陳文豪 [TSMC]

WA2 - UPF Solutions
Experience Sharing on IC Compiler Adoption
Author(s): 林宗毅 Eric Lin [Etron]
Presentation

Low Power Design & Verification for PACDSP (Technical Committee Award Honorable Mention)
Author(s): C. Y. Liao [ITRI]
PaperPresentation

Low Power Verification Methodology for a hierarchical design with handicapped UPF
Author(s): Kasen Chuang, Nigel Tan, Vincent Chan, Chek Leong [TSMC]
PaperPresentation

WA3 - Fast SPICE
Flash Memory IR/EM analysis using HSIMPlus
Author(s): C.J. Yeh [Macronix]
PaperPresentation

How to verify design reliability issue with HSIM
Author(s): 詹偉閔 Gary Chan [TSMC]
Presentation

WA4 - FPGA Solutions
Advanced RTL debug Solution for Peripheral Device Interface
Author(s): Chih-Ming Chen [Nuvoton]
Presentation

Experience Sharing of Successful debugging cases in FPGA system verification
Author(s): Jerry Lin [Faraday]
Presentation

Prototyping Performance Comparison on MIMO Project Using HAPS34 and HAPS54
Author(s): Feng-Chi Chen [ITRI]
Presentation

SNPS USB 3.0 Prototyping Experience Sharing on HAPS52
Author(s): Rex Lin [Realtek]
Presentation

WB1 - ICC/Lynx
A Case Study: In-Design Rail and In-Design Timing by using ICC
Author(s): 陳建良, 黃柏馨, 許家玲 [Ali]
Presentation

Core-Package-PCB co-simulation with Reduced-Core-Model
Author(s): 許聖裕 [Hitmax]
Presentation

Easy to access UMC technology by Lynx FRS Design System
Author(s): Felix Jen [UMC}
Presentation

In-Design Signoff-Quality DRC & Fill using IC Validator within IC Compiler
Author(s): Tse-Hung Liu [UMC]
Presentation

WB2 - UPF Solutions
MVRC/MVSIM enables TSMC N28/N40 Product Qualification Vehicle (PQV) chip design
Author(s): Jasper Changchien [TSMC]
Presentation

WB3 - Fast SPICE/Co-sim/Extraction
Analog Reference Flow
Author(s): 黃慕真 [TSMC]
Presentation

Power Characterization With NanoTime
Author(s): Jack Liu, C.W. Su [TSMC]
Presentation

SOC & IP System Verification Methodology with Nanosim-VCS Cosim
Author(s): Yu-Hua Huang [Novatek]
Presentation

WB4 - FPGA/IP
Performance Matched Design for Multi-level Memory Hierarchy in a Multi-core SoC
Author(s): James Lai [Andes]
Presentation

System Validation using IP-XACT standards
Author(s): Rajesh Chirumamilla [ARM]
Presentation

Publication Only
Scan Compression Experience using DFTMAX
Author(s): Duke Lin, Roger Lin [Phison]
Paper

Tutorials
TA1-ICC/Lynx
Predictable Schedule and Instant Access to Advanced Technology with Lynx Design System
Author(s): Synopsys Technical Experts
Tutorial

TA3-VMM
VMM 1.2 Tutorial
Author(s): Synopsys Technical Experts
Tutorial

TB1-ICC
IC Compiler Feasibility Flow
Author(s): Synopsys Technical Experts
Tutorial

Streamline text shorts detection with IC Validator
Author(s): Synopsys Technical Experts
Tutorial

TB2-Synthesis/Low Power Synthesis
Galaxy RTL: Design Compiler Family 2010.03 Update
Author(s): Synopsys Technical Experts
Tutorial

WA1 - ICC
IC Compiler Planning and Implementation of Large Hierarchical Designs
Author(s): Synopsys Technical Experts
Tutorial

WA2 - UPF Solutions
Low Power Verification
Author(s): Synopsys Technical Experts
Tutorial

WA3 - Fast SPICE
CustomSim-CircuitCheck (CCK)
Author(s): Synopsys Technical Experts
Tutorial

WB2 - UPF Solutions
Low Power Multi-Voltage Design Implementation Methodology using the IEEE 1801 (UPF) Standard
Author(s): Synopsys Technical Experts
Tutorial

WB3 - Fast SPICE/Co-sim/Extraction
AMS Verification Solutions
Author(s): Synopsys Technical Experts
Tutorial

WB4 - FPGA/IP
HAPS-60 -- The Next-generation Rapid Prototyping Platform Introduction
Author(s): Synopsys Technical Experts
Tutorial

The latest protocols and cooperation with Synopsys DesignWare IP solution
Author(s): Synopsys Technical Experts
Tutorial