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| User Papers and Presentations |
| TA1-ICC/Lynx |
Low power CTS technique using optimal ICG placement (Best Paper Award)
Author(s): 陳軍, Dhaval Bhatia,王孝誠, 張裕東 [Mediatek] |
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Multi-Media design put into use ICC ILM flow
Author(s): ShiZhi [Realtek] |
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| TA2-STA/Test/Lynx |
3D IC Implementation
Author(s): 李鴻禧、陳振岸、陳繼展 [工業技術研究院] |
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Boost PrimeTime Productivity Using Multicore
Author(s): Eason Lin [Via] |
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Reduce Power Consumption in High Performance IP with Synopsys Designware minPower Solution
Author(s): Mexx Lin [Faraday] |
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Scan Test Power Reduction Using Power-aware ATPG (Best Paper Award)
Author(s): Pei-Ying Hsueh, Shuo-Fen Kuo, Ying-Yen Chen, Jin-Nung Lee, Chi-Feng Wu [Realtek] |
|
| TA3-VMM |
Adopting vmm_subenv in SOC projects
Author(s): Cheng Chung Yuan, An Hsiao Cheng [Realtek] |
|
Methodology of Executable Verification Plan (Technical Committee Award Honorable Mention)
Author(s): Shang-Wei Tu [Sunplus] |
|
| TB3-VMM/ESL |
ESL Virtual Platform for System Performance Enhancement (Best Paper Award)
Author(s): Jen-Chieh Yeh [ITRI] |
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Using VMM to Address DTV Transport Processor Verification Challenges
Author(s): Temin Kuo [Realtek] |
|
| WA1 - ICC |
N40 DFM Implementation Flow
Author(s): Ken Wang [TSMC] |
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Reference Flow
Author(s): 陳文豪 [TSMC] |
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| WA2 - UPF Solutions |
Experience Sharing on IC Compiler Adoption
Author(s): 林宗毅 Eric Lin [Etron] |
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Low Power Design & Verification for PACDSP (Technical Committee Award Honorable Mention)
Author(s): C. Y. Liao [ITRI] |
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Low Power Verification Methodology for a hierarchical design with handicapped UPF
Author(s): Kasen Chuang, Nigel Tan, Vincent Chan, Chek Leong [TSMC] |
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| WA3 - Fast SPICE |
Flash Memory IR/EM analysis using HSIMPlus
Author(s): C.J. Yeh [Macronix] |
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How to verify design reliability issue with HSIM
Author(s): 詹偉閔 Gary Chan [TSMC] |
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| WA4 - FPGA Solutions |
Advanced RTL debug Solution for Peripheral Device Interface
Author(s): Chih-Ming Chen [Nuvoton] |
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Experience Sharing of Successful debugging cases in FPGA system verification
Author(s): Jerry Lin [Faraday] |
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Prototyping Performance Comparison on MIMO Project Using HAPS34 and HAPS54
Author(s): Feng-Chi Chen [ITRI] |
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SNPS USB 3.0 Prototyping Experience Sharing on HAPS52
Author(s): Rex Lin [Realtek] |
|
| WB1 - ICC/Lynx |
A Case Study: In-Design Rail and In-Design Timing by using ICC
Author(s): 陳建良, 黃柏馨, 許家玲 [Ali] |
|
Core-Package-PCB co-simulation with Reduced-Core-Model
Author(s): 許聖裕 [Hitmax] |
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Easy to access UMC technology by Lynx FRS Design System
Author(s): Felix Jen [UMC} |
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In-Design Signoff-Quality DRC & Fill using IC Validator within IC Compiler
Author(s): Tse-Hung Liu [UMC] |
|
| WB2 - UPF Solutions |
MVRC/MVSIM enables TSMC N28/N40 Product Qualification Vehicle (PQV) chip design
Author(s): Jasper Changchien [TSMC] |
|
| WB3 - Fast SPICE/Co-sim/Extraction |
Analog Reference Flow
Author(s): 黃慕真 [TSMC] |
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Power Characterization With NanoTime
Author(s): Jack Liu, C.W. Su [TSMC] |
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SOC & IP System Verification Methodology with Nanosim-VCS Cosim
Author(s): Yu-Hua Huang [Novatek] |
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| WB4 - FPGA/IP |
Performance Matched Design for Multi-level Memory Hierarchy in a Multi-core SoC
Author(s): James Lai [Andes] |
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System Validation using IP-XACT standards
Author(s): Rajesh Chirumamilla [ARM] |