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| User Papers and Presentations |
| User Sessions |
Advanced DFM Methodology based on TCAD
Author(s): Francis Benistant, Li Yisuo [Chartered Semiconductor Manufacturing] |
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Analysis of Design Complexity of Datapaths
Author(s): Satzoda Ravi Kumar, Quek Kai Hock, Dr. T. Srikanthan [Nanyang Technological University, Singapore] |
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ASIC Backend Flow using Synopsys Astro
Author(s): Seong Chew, Lim [Integrated Circuit Design Services Sdn. Bhd.] |
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Co-Existing with Legacy Verification Environments in a Vera Testbench
Author(s): Peter Byrne, Kiril Uzunov, Nicholas Aschberger, Bernard Gunther [Australia SoC Technology Centre, Freescale Semiconductor, Adelaide, Australia] |
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Formal Verification in FPGA Synthesis Flow; DC-FPGA & Formality
Author(s): Kee Chun Cheng, Cadman [Creative Technology Ltd] |
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Full Chip Transistor-Level Post-layout simulation and Power Analysis in SoC Design
Author(s): Dong Wei, Lo Han Cheng [Infineon Technologies Asia Pacific Pte. Ltd] Lei Zhang [Infineon Technologies Xi'an Co. Ltd] |
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Ring Oscillator Phase Noise Simulation by Hspice RF
Author(s): Li Yi [FTD Solutions Pte Ltd] |
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Scan Failure Diagnosis using TetraMAX
Author(s): SONG Yun Mei, ZHAO Fang Fang, TAO Ta Wei, MAI Zhi Hong, Benjamin LAU, Jeffrey LAM [Chartered Semiconductor Manufacturing Limited] |
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Uncertainties and Pessimism in PrimeTime/PrimeTime-SI Analysis (1st Place - Best Paper)
Author(s): Sidney Ng, Christophe Bouquet, Anand Shirwal, Siew-Kuan Tham [Infineon Technologies, Singapore] |
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Using Formality to Implement and Verify an ECO Change in an Optimized Netlist (2nd Place - Best Paper)
Author(s): Mark Tang Tuck Houng [O2 Micro Pte Ltd] |
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Using FPGA for Random Verification
Author(s): Andy Chang, Kadambi Ranga, Teo Aik Hwee [Infineon Technologies] |