SNUG Singapore 2004 Proceedings
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User Papers and Presentations
User Sessions
An Automated Method to Fix Hold Violations for Cell-Based Design (1st Place - Best Paper)
Author(s): Soon Chieh Lim [Intel Microelectronics Malaysia Sdn Bhd]
PaperPresentation

Digital Design Flow for Spread Spectrum Clocking (SSC)
Author(s): Tao Yong Hong (Tony) [FTD Solutions Pte Ltd]
PaperPresentation

Hercules Layout Verification Qualification Methodology
Author(s): Kuan Yeow Leong [Altera Corporation]
PaperPresentation

Implementation of Joint-Detection Receiver on ST122 DSP for TD-SCDMA Systems
Author(s): S. W. Oh, N. Promsatawong [STMicroelectronics Asia Pacific] M. Sun, J. Santos [Institute for Infocomm Research]
PaperPresentation

Reducing Risks in Digital Design Through FPGA Prototyping
Author(s): King Ou, Jan-Sian Tai [Altera Corporation]
PaperPresentation

Speed Profiling - Static Timing Analysis visualisation in Complex IC designs
Author(s): Ben Eckermann [Motorola Australia Pty Ltd]
PaperPresentation

Statistical Timing Analysis: The What, Why and How?
Author(s): Sidney Ng [Infineon Technologies Asia Pacific]
PaperPresentation

System On Chip Concurrent Simulation using VERA
Author(s): Mahin Yusuf Ainalikudy, Sanjay Pawar [Hewlett-Packard Singapore]
PaperPresentation

Timing Constraints: The Hidden Dimension of Design Challenges for UDSM SoC
Author(s): Lei Zhang, Kim Wee Ng, Lei Zhang (Rachael), Hui Fu [Infineon Technologies Asia Pacific]
PaperPresentation

Using Unified Test DRC and ILM+CTL models for Physical Hierarchical Scan Synthesis in a Complex SOC
Author(s): Jagan Thinakaran [STMicroelectronics APDC]
PaperPresentation


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