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| User Papers and Presentations |
| MA02 - Challenges and Strategies for Advanced Designs |
High Performance SoCs: Effective Strategies for achieving Optimal Performance, Power & Faster Design Closure
Author(s): Santhosh Pillai, Sarita Baswant, Ashwani Gupta, Prasanth Koduri, Vi Nguyen, Sowjanya Mukka - Samsung Semiconductors |
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Routing at 20nm - It is Challenging but Achievable
Author(s): Chad Hale - ARM |
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| MA04 - Verification with OVM/UVM Methodologies |
OVM/UVM Scoreboards - Fundamental Architectures
Author(s): Cliff Cummings - Sunburst Design, Inc. |
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Reset Testing Made Simple with UVM Phases
Author(s): Ben Chen, Brian Hunter - Cavium, Rebecca Lipon - Synopsys |
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| MA06 |
MA06-A "No Man's Land" - Constraining Async Clock Domain Crossings (3rd Place - Best Paper, Technical Committee Award)
Author(s): Paul Zimmer - Zimmer Design Services |
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| MA06-B |
MA06-B Efficient Timing Constraint Analysis and Debug using PrimeTime-GCA (Technical Committee Award Honorable Mention)
Author(s): Peter Lindberg - LSI Corp. |
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| MA08 AMS for FinFET and 3DIC |
A New SPICE Simulation Approach for 3D IC Integration
Author(s): Susan Wu, Jianlin Wei - Xilinx; Horace Lam - Synopsys |
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Planar MOSFET to FinFET: A User Experience With HSPICE, FineSim, StarRC, RAPID3D, RC3
Author(s): Tom Mahatdejkul, Ling Chien, Sreenivas Aluru - ARM |
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| MB01 ARM GPU Implementation at 20nm |
Proving the 20nm Implementation Ecosystem Using an ARM Mali GPU with a Full Galaxy Tool Flow
Author(s): Shawn Hung - ARM |
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| MB02 Advanced CTS Methodologies |
Holistic Clocking Methodology that Supports Low-Skew (<20ps) and High-Speed (>1.5GHz) Clocking with Low Power for 28nm Designs
Author(s): Anand Iyer, Kedar Kulkarni, Tim Kasper, Abhishek Kumar - Advanced Micro Devices, Inc.; Denise Powell, Chirakala Chinavenkata - Synopsys |
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Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler
Author(s): Can Sitik, Baris Taskin - Drexel University |
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| MB06 Optimizing Extraction Performance and Accuracy |
Optimizing Extraction Performance: Samsung Success with StarRC Simultaneous Multi-Corner Extraction
Author(s): Santhosh Pillai - Samsung |
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| MB08 |
MB8-A Using IBIS-AMI Models in HSPICE
Author(s): David Banas - Altera |
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| MB08-B |
MB8-B Top-Down Post Full-Chip Verification for SRAM Boundary Simulation with FinesimPro
Author(s): Garry Tse - SPANSION Inc.; Danny Cheng, Synopsys |
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| MC02 |
MC2-A Floorplanning and Layout Feasibility with Multi-Instance Partitions
Author(s): Sanjay Balasubramanian, Priya Joshi, Pratik Lunavat - Intel Corp. |
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| MC02-B |
MC2-B Achieving Predictable Timing in ASIC Flow using Design Compiler Graphical/IC Compiler for High Performance Designs
Author(s): Venkataraman Srinivasagam - Cisco Systems Inc. |
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| MC03 |
MC3-A Hardware Redundancy and Design Fault Tolerance and their Applicability to Chip Design
Author(s): Kurt Baty - WSFDB Consulting |
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| MC03-B |
MC3-B Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification (1st Place - Best Paper)
Author(s): Don Mills - Microchip Technology; Stuart Sutherland - Sutherland HDL, Inc. |
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| MC04 |
MC4-A VISA: A State-Based, Hierarchical, Architecture-Independent Random Test Generation Environment for High-Performance Multiprocessors
Author(s): Neil McKenzie, Michael Sedmak, Adam Snay, Chris Weller - Advanced Micro Devices, Inc. |
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| MC04-B |
MC4-B Random Stability in SystemVerilog
Author(s): Doug Smith - Doulos, Inc. |
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| MC06 Extraction for New Transistor Nodes and Technologies |
Double Patterning Aware Extraction Flows For Digital Design Sign-Off in 20/14nm (2nd Place - Best Paper)
Author(s): Adrian Au Yeung, Steven Chan, Hendrik Mau, Rick Monga, Tamer Ragheb, Venkat Ramasubramanian, Richard Trihy - GLOBALFOUNDRIES |
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Planar MOSFET to FINFET: A User Experience With HSPICE, FineSim, StarRC, RAPID3D, RC3
Author(s): Tom Mahatdejkul, Ling Chien, Sreenivas Aluru- ARM |
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| TA04 |
TA4-A Transaction Based Assertion for Transaction Level Coverage, Property and Protocol Checking
Author(s): Sakar Jain, Thinh Ngo - Freescale Semiconductor, Inc. |
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| TA04-B |
TA4-B Sub-cycle Functional Timing Verification using SystemVerilog Assertions
Author(s): Anders Nordstrom - Verilab |
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| TB04 |
TB4-A Challenges with Design and Verification of State Retention in a Complex Low-Power SoC
Author(s): Yushi Tian - Broadcom Corp.; Amir Nilipour, Ajay Thiriveedhi - Synopsys |
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| TB04-B |
TB4-B Formal Verification of Floating-Point Arithmetic Datapath Block
Author(s): Leonard Rarick - Imagination Technologies, Inc. Ajit Limaye - Synopsys |
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| TB04-C |
TB4-C A Reusable Verification Testbench Architecture Supporting C and UVM Mixed Tests
Author(s): Richard Tseng - Qualcomm |
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| TB06 Leakage Recovery with PrimeTime |
Leakage Recovery across Multiple Timing Scenarios
Author(s): Russell Vickers - Intel |
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| TB07 SoC Architecture Optimization |
SoC Architecture Analysis and Optimization Using Synopsys Platform Architect MCO
Author(s): Tom Ajamian - Analog Devices, Inc. |
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| TC01 |
TC1-A Advanced Retention Power Gating: Unlocking Opportunistic Leakage Savings in High Performance Mobile SoCs - Technical Committee Award, Honorable Mention (Technical Committee Award Honorable Mention)
Author(s): John Biggs, David Flynn, James Myers - ARM |
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| TC02 Design Environments using Lynx |
Standardized Design Environment and Methodologies Enable Simultaneous Implementation of 28nm Designs on a Single Flow
Author(s): Cyrille Thomas - Bull SAS |
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Using the Lynx Design System to Lower the Cost of Bringing up a New Flow on a New Node
Author(s): Simone Borri, Christian Eichrodt, Pierre-Marie Signe - Abilis Systems; Riccardo Giordani - Synopsys |
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| TC03 Small Delay Defect Model and Advanced Debugging Test |
Advanced TetraMAX Debugging Techniques for AMD's High-Performance Cores
Author(s): Martin Amodeo, Thomas Clouqueur, Jan Ness - Advanced Micro Devices, Inc.; Tim Ayres, Lori Schramm, Tim Yuan - Synopsys |
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Improving At-Speed Test Quality with the Small Delay Defect Model
Author(s): Jon Colburn, Dheepakkumaran Jayaraman, Bala Tarun Nelapatla, Arvind Vinod - NVIDIA |
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| TC06 Mode-Merging using PrimeTime |
Automated Mode Merging of Timing Constraints using PrimeTime
Author(s): Harish Aepala, Nick Oleksinski, Bruce Zahn - LSI Corp. |
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| TC09 Increasing ARC Performance and Reducing Power |
Increasing Performance and Reducing Power through Memory Request Optimization
Author(s): Gregg Recupero - Performance-IP |
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| WA05 High Performance Computing |
High Performance Computing for Silicon Design
Author(s): Shesha Krishnapura - Intel |
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| WA06 Noise Analysis |
Digital->Analog Noise Detection (DANDy)
Author(s): Jason Rziha, Vardhini Muralidaran - Microchip Technology |
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Transistor-Level Timing and Noise Analysis of Peripheral Logic of High Speed Memory Design
Author(s): Johnie Au, Sunilkumar Koduru, Jun Li - Cypress Semiconductor; Sahil Bargal - Synopsys |
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| WB05 Managing and Optimizing Compute Infrastructure |
Advanced Load Balancing and Resource Sharing Solutions
Author(s): Robert Veltman, Vikash Tyagi - SanDisk |
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HP’s Common Engineering Environment for VLSI design
Author(s): Jeff Quigley - Hewlett Packard |
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| WB06 Characterization Solutions |
SiliconSmart Flow for Characterization Production Runs
Author(s): Beibei Ren - NVIDIA; Manjunath B Thimmachary - Synopsys |
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| WC05 Storage Optimization |
VCS Acceleration Enabled by Storage Optimization
Author(s): Ravi Poddar/ Bikash Roy Choudhury - NetApp |