SNUG San Jose 2011 Proceedings

2011|2010
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Complete Proceedings


User Papers and Presentations
MA1 User - DFM/Routing
Routing Solutions for CPU Design on Advanced Process Nodes
Author(s): Victoria Kolesov, Atul Walimbe [Intel Corp.]
PaperPresentation

Using Synopsys IC Compiler for DFM Optimization at 28nm
Author(s): Rainer Mann, Ulrich Hensel, Vito Dai [GLOBALFOUNDRIES], Jens Peters [Synopsys, Inc.]
PaperPresentation

MA4 User - Constraint Solver Performance and Coverage Merging
An Automated Iterative Approach to VCS Coverage Merge
Author(s): Christopher Hsiong, Lloyd Cha [Advanced Micro Devices, Inc.], Paul Graykowski, Padmaraj Ramachandran, Vijay Akkaraju [Synopsys, Inc.]
PaperPresentation

Attacking Constraint Complexity in a Large Scale Networking ASIC Verification Environment
Author(s): Srinath Atluri, Ben Chen, Harish Krishnamoorthy [Cisco Systems, Inc.], Alex Wakefield, Dhiraj Goswami, Rebecca Lipon, Eduardo Dubovoy [Synopsys, Inc.]
PaperPresentation

MB2 User & Tutorial - Custom Designer, PDKs and StarRC
Successful Migration and Tapeout of a Large Complex Design by Foveon Using Custom Designer
Author(s): Scott Taft [Foveon], Amit Patel, Ravishankar Bhaskaran [Synopsys, Inc.]
PaperPresentation

MB3 User - PrimeTimePX
A New Approach for Measuring Dynamic Voltage Drop Effect using PrimeTimePX and PrimeRail on a Design Routed by IC Compiler
Author(s): Johnie Au [Cypress Semiconductor]
PaperPresentation

Early Time-Based Block Specific Power Analysis Methodology Using PrimeTimePX
Author(s): Sharat Shekar [Drexel University], Michael Bowen [LSI Corp.]
PaperPresentation

MB4 User - SystemVerilog and VMM
Dynamic Tree Model for USB 3.0-xHCI Host Verification Using SystemVerilog
Author(s): Vikas Kulkarni [Innovative Logic]
PaperPresentation

Functional Coverage Driven VMM Verification Scalable to 40G/100G Technology
Author(s): Craig Baker, Amit Baranwal [ViaSat Inc.]
PaperPresentation

MB6 User - MOSFET & HSPICE
28nm MOSFET Aging Modeling and Simulation Using HSPICE and HSIM MOSRA
Author(s): Liping Li, Jeff Watt [Altera Corp.], Joddy Wang, Bogdan Tudor, Joan Peng, Weidong Liu [Synopsys, Inc.]
PaperPresentation

Simple Method for Statistical Variation MOSFET Model Qualification with HSPICE
Author(s): Tom Mahatdejkul [ARM Physical IP]
PaperPresentation

MC1 User & Panel - Architecture Feasibility & Lynx Design System
Early Architecture Feasibility Analysis using IC-Compiler
Author(s): Krishna Kumar Gundavarapu [Cisco Systems, Inc.]
PaperPresentation

MC4 User - Verification Methodology & Magellan
A Verification Methodology for Safety-Critical Applications
Author(s): Massimiliano Corba, John Sotiropoulos, Matthew Muresan [Draper Laboratory]
PaperPresentation

Automatic Coverage Closure using Magellan
Author(s): Narayan Kulshrestha, Prosenjit Chatterjee, Srihari Sridharan [NVIDIA Corp], Mandar Munishwar [Synopsys, Inc.]
PaperPresentation

MC5 User - FPGA Design
A Methodology for Creating Reusable Design Blocks Targeting FPGA Devices (1st Place - Best Paper)
Author(s): Phil Simpson, Jennifer Stephenson [Altera Corp.]
PaperPresentation

Synopsys and Xilinx Hierarchical Design Flows
Author(s): Kate Kelley, Frederic Rivoallon [Xilinx, Inc.]
PaperPresentation

MC6 User - HSPICE & CustomSim-XA
Power Delivery Analysis and Optimization on Complex ASIC Packages and Dies with HSPICE
Author(s): Amir Motamedi [Juniper Networks], Sumit Vishwakarma [Synopsys, Inc.]
PaperPresentation

Using CustomSim-XA in the Construction of a Hybrid Tree-Mesh Clock Distribution Network
Author(s): Nikhil Jayakumar, Dave Murata, Valery Kugel [Juniper Networks], Sumit Vishwakarma [Synopsys, Inc.]
PaperPresentation

TA4 User - VCS Compile and Runtime Improvements
Improving Verification Throughput for ATOM™ SOC by Design Partitioning
Author(s): Gayathri Manikutty, Dhrubajyoti Kalita [Intel Corp.]
PaperPresentation

Techniques for Improving Simulation Performance in Microprocessor Verification
Author(s): Neil McKenzie, Mitchell Poplingher, Lloyd Cha, Dhruba Chandra [Advanced Micro Devices, Inc.], Vijay Akkaraju [Synopsys, Inc.]
PaperPresentation

TB1 User - IC Compiler & Hierarchical Design
Multi-Level Physical Hierarchy (Top Down or Bottom Up?)
Author(s): Adrian Javelo, Kevin Huang, Michael Lai, James Deng, Michael Zheng [Altera Corp.]
PaperPresentation

Using ICC’s Advanced Features to Enable Top-Level Design of Complex Hierarchical Chips
Author(s): Khalil Siddiqui [Juniper Networks]
PaperPresentation

TB3 User - PrimeTime DMSA & AOCV
Accelerated Timing Closure using PrimeTime DMSA Based Auto-ECO Flow
Author(s): Venkataraman Srinivasagam [Cisco Systems Inc.]
PaperPresentation

Advanced OCV Timing Derating Experience (Technical Committee Award)
Author(s): Alexander Tetelbaum , Rich Laubhan [LSI Corp.], David Keyser [Synopsys, Inc.]
PaperPresentation

TB5 User - FPGA Prototyping
Implementing JTAG using the CHIPit UMRBus (Best First-Time Presenter)
Author(s): Gary Gibson [Cray Inc.]
PaperPresentation

Maximizing HW Resources in an Integrated FPGA Partitioning Flow
Author(s): Fernando Martinez [NVIDIA]
PaperPresentation

TC1 User - Low Power & Timing Closure
Implementing a High-Speed, Low-Power ARM Cortex A9 (3rd Place - Best Paper)
Author(s): Bob Turner [Broadcom Corp.], Nish Balaji [Synopsys, Inc.]
PaperPresentation

Signoff-Driven Leakage-Power Optimization
Author(s): Darren Engelkemier, Steven Yang [Aquantia Corp.]
PaperPresentation

Unique Approach to High Speed Read FIFO Timing Closure in DDR2/3 Sub-System
Author(s): Cyrus Cheung, Eric Persson [LSI Corp.]
PaperPresentation

TC3 User & Tutorial - Galaxy Constraint Analyzer
A Case for Adopting Galaxy Constraint Analyzer (2nd Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Richard Bishop [Advanced Micro Devices, Inc.]
PaperPresentation

TC4 Tutorial & User -Low Power Verification
Low-Power Verification Methodology
Author(s): Div Bole, Kesava Talupuru [MIPS Technologies]. Shawn Honess [Synopsys, Inc.]
PaperPresentation

WA2 User - Test
AMD Latch-based Design Methodologies with TetraMAX ATPG (Technical Committee Award Honorable Mention)
Author(s): Martin Amodeo, Dwight Elvey [Advanced Micro Devices, Inc.], Aurelia De Colle, Tim Ayres [Synopsys, Inc.]
PaperPresentation

ATPG Capacity Evaluation and Test Architecture Results for a 28nm Design
Author(s): Yan Dong, Amit Majumdar, Ken Pham [Advanced Micro Device, Inc.], Aurelia DeColle,Lori Schramm, Don Skinner [Synopsys, Inc.]
PaperPresentation

Using Non-Scan Cell Support to Improve DFT Results
Author(s): Jonathon E Colburn [NVIDIA]
PaperPresentation

WB3 User &Tutorial - NanoTime
Advanced Timing Model Generation Using NanoTime - Tips & Tricks
Author(s): Zafar Hasan, George Kokai [NVIDIA], Mohammad Bahri [Synopsys, Inc.]
PaperPresentation

White Paper
WC4 White Paper
Formal Verification and Validation of High-Level Optimizations of Arithmetic Datapath Blocks
Author(s): Theo Drane [Imagination Technologies, Ltd.], Himanshu Jain [Synopsys, Inc.]
PaperPresentation

Tutorials
MA2 Tutorial
Synopsys Custom Design Solution
Author(s): Marc Swinnen, Fredrik Ivarsson [Synopsys, Inc.]
Tutorial

MA3 Tutorial
Analyzing the Effectiveness of Multi-Voltage Power Saving Techniques with PT-PX
Author(s): Maria Tovey [Synopsys, Inc.]
Tutorial

MA6 Tutorials
Parallel Compute Technology Advantage in HSPICE
Author(s): Harald Von Sosen [Synopsys, Inc.]
Tutorial

Transient Noise Analysis in HSPICE
Author(s): Tracy Barclay, Scott Wedge [Synopsys, Inc.]
Tutorial

MB1 Tutorials
IC Compiler 2010.12 Feasibility Focused Update
Author(s): Mehrang Razzaz [Synopsys, Inc.]
Tutorial

IC Compiler Physical Datapath
Author(s): Shubharthi Datta [Synopsys, Inc.]

MB2 User & Tutorial - Custom Designer, PDKs and StarRC
Using StarRC in Custom Layout Environment: From PDKs to Rapid3D Extraction
Author(s): Omar Shah [Synopsys, Inc.]
Tutorial

MB5 Tutorial
FPGA Flows from Top-Down to Bottom-Up
Author(s): Will Cummings [Synopsys, Inc.]
Tutorial

MC2 Tutorial
Addressing Physical Verification Challenges at 28nm and Below with IC Validator
Author(s): Ron Duncan [Synopsys, Inc.]
Tutorial

TA2 Tutorial
DC 2010.12 Update
Author(s): Bob Wiegand, Bob Hatt [Synopsys, Inc.]
Tutorial

TA3 Tutorial
Faster Multi-Scenario ECO Fixing in PrimeTime
Author(s): Troy Epperly [Synopsys, Inc.]
Tutorial

TA5 Tutorial
Partitioning and Reconnecting: A Key Prototyping Expertise
Author(s): Joseph Marceno, Doug Amos [Synopsys, Inc.]
Tutorial

TA7 Tutorial
Scaling High-Level Synthesis for Complex Image and Video Processing Designs
Author(s): Chris Eddington, Craig Gleason [Synopsys, Inc.]
Tutorial

TB2 Tutorial
Eliminating Late-Stage Manual Fixes with In-Design Physical Verification
Author(s): Ron Duncan [Synopsys, Inc.]
Tutorial

TB4 Tutorial
VCS Productively Tools and Technologies that Help Reduce the Ever-Growing Verification Cycle
Author(s): Latha Venkatachari [Synopsys, Inc.]
Tutorial

TB6 Tutorials
Best Practices in Software License Management and the Challenges of the Cloud
Author(s): Dan Griffith [Dan Griffith Consulting]
Tutorial

Synopsys Licensing: Optimizing Your License Infrastructure for Performance and Reliability
Author(s): Jesse Flores [Synopsys, Inc.]
Tutorial

TB7 Tutorial
Using Embedded Software to Accelerate Verification
Author(s): Filip Thoen, Achim Nohl, Frank Schirrmeister [Synopsys, Inc.]
Tutorial

TC2 Tutorial
IC Compiler 2010.12 Release Update
Author(s): Vibhu Veerabadrappa [Synopsys, Inc.]
Tutorial

TC3 User & Tutorial - Galaxy Constraint Analyzer
Galaxy Constraints Analyzer: Advanced Constraints Debugging
Author(s): Lionel Corbet [Synopsys, Inc.]
Tutorial

TC4 Tutorial & User -Low Power Verification
New Technologies to Address Low Power Verification Accuracy and Productivity
Author(s): Prapanna Tiwari [Synopsys, Inc.]
Tutorial

TC5 Tutorial
Enhancing an IP Validation Environment Utilizing FPGA-Based Prototyping
Author(s): Aaron Yang, Torrey Lewis, Mat Loikkanen [Synopsys, Inc.]
Tutorial

TC6 Tutorials
GPU Acceleration for Engineering Applications
Author(s): Srinivas Kodiyalam, Paulius Micikevicius [NVIDIA]
Tutorial

Intel Design Computing Strategies & Solutions
Author(s): Shesha Krishnapura [Intel Corp.]

TC7 Tutorial
Replacing Fixed Hardware Blocks with Custom Processors
Author(s): Drew Taussig, Achim Nohl, Frank Schirrmeister [Synopsys, Inc.]
Tutorial

WA1 Tutorial
IC Compiler, Fast Hierarchical Design Exploration, Planning, Block Implementation and Top-Level Closure
Author(s): Frank De Meersman, Simon Koval [Synopsys, Inc.]
Tutorial

WA3 Tutorial
ESP Power Intent Verification
Author(s): Dave Hedges [Synopsys, Inc.]
Tutorial

WA4 Tutorial
New Levels of Verification IP Productivity
Author(s): Kulanthivelu Veluchamy [Synopsys, Inc.]
Tutorial

WA5 Tutorial
Integrating MIPI Interfaces for Camera and Display Peripherals in SoCs (with case study by OSI)
Author(s): Hans Bouwmeester [Open-Silicon, Inc], Miguel Falcao Sousa [Synopsys, Inc.]
Tutorial

WA6 Tutorial
How Chip Designers Can Benefit From Low-Power Memory Design Techniques
Author(s): Prasad Saggurti [Synopsys, Inc.]
Tutorial

WA7 Tutorial
USB 3.0 IP: The Path from Concept to Certified Products
Author(s): Bob Lefferts [Synopsys, Inc.]
Tutorial

WB1 Tutorial
New Multi-Voltage Power Optimization Techniques to Address Power Reduction During Design Implementation
Author(s): Somil Ingle, Gloria Chen [Synopsys, Inc.]
Tutorial

WB2 Tutorial
DFTMAX Compression, TetraMAX ATPG, and the STAR Memory System Updates
Author(s): Adam Cron, Gevorg Torjyan [Synopsys, Inc.]
Tutorial

WB3 User &Tutorial - NanoTime
NanoTime CCS Noise Model Generation and HSPICE Recalibration in the Custom Designer Environment
Author(s): Chad Lawrence [Synopsys, Inc.]
Tutorial

WB4 Tutorial
New Advancements in Methodology to Improve Verification Turn-Around-Time
Author(s): Janick Bergeron, Eduardo Dubovoy [Synopsys, Inc.]
Tutorial

WB5 Tutorial
Reducing Static Power Consumption in Advanced SoC Designs Using Long and Multi-Channel Logic Libraries
Author(s): Deepak Sherlekar [Synopsys, Inc.]
Tutorial

WB6 Tutorial
Configuring DesignWare ARC Processors To Your Embedded or Host SoC Application
Author(s): Martin Kite [Synopsys, Inc.]
Tutorial

WB7 Tutorial
How To Avoid Design Pitfalls and Ensure a Successful DDR PHY Implementation
Author(s): Mark Arseneau [Synopsys, Inc.]
Tutorial

WC1 Tutorial
IC Compiler Design Planning with Template-Based Power Network Synthesis
Author(s): Dale Russell [Synopsys, Inc.]
Tutorial

WC3 Tutorial
StarRC 2010.12: Faster Extraction for 28-nm Designs
Author(s): TBD [Synopsys, Inc.]
Tutorial

WC5 Tutorial
Designing Mobile Multimedia SoCs with Low-Power, High-Performance IP Solutions
Author(s): James Wu [Synopsys, Inc.]
Tutorial

WC6 Tutorial
Implementing Low-Power Designs with DesignWare minPower Components
Author(s): Fred Roberts [Synopsys, Inc.]
Tutorial

WC7 Tutorial
Addressing the Challenges of Designing an AMBA-based SoC with a PCI Express Interface
Author(s): Frank Kavanagh [Synopsys, Inc.]
Tutorial

Panel Presentation
MC1 User & Panel - Architecture Feasibility & Lynx Design System
Achieving More Predictable Design Closure with Pre-Validated Flows & Advanced Visualization Tools
Author(s): Dennis Lewis [Integrated Device Technology, Inc.], Mogens Isager [Oticon, Inc.], Glenn Dukes [Synopsys, Inc.]

WC2 Panel
How Much Test Coverage is Enough?
Author(s): Savita Banerjee [LSI Corp.], Subhasish Mitra [Stanford University], Joseph Reynick [eSilicon], Chafik Behidj [GLOBALFOUNDRIES], Yervant Zorian [Synopsys, Inc.]

Speech
Guest Speaker: Kwang-Hyun Kim, Executive Vice President, Samsung Electronics
Consumer-Driven Innovation in SoC Design
Author(s): Dr. KH Kim [Samsung Electronics]

Guest Speaker: Godwin Maben, Principal Applications Consultant, Synopsys, Inc.
Low Power Design: How Long Until We Hit the Wall?
Author(s): Godwin Maben [Synopsys, Inc.]

Keynote Speaker: Aart de Geus, Chairman of the Board and CEO, Synopsys, Inc.
Fast Forward! Designing the future of semiconductors
Author(s): Aart de Geus [Synopsys, Inc.]
Video

Guest Presentation
Design Compiler Product Luncheon
Hot, New Technology Accelerates Design Development and Implementation
Author(s): Tsutomu Fujii [Panasonic], Atul S. Walimbe [Intel], Giancarlo Sada [STMicroelectronics], Antun Domic [Synopsys, Inc.]
Presentation