SNUG San Jose 2010 Proceedings

2011|2010
Sort proceedings by:


Complete Proceedings


User Papers and Presentations
MA2 User - Constraints and Power Challenges in Verification
Formal Methods to Verify the Power Manager for an Embedded Multiprocessor Cluster
Author(s): Kesava Talupuru [MIPS Technologies, Inc.]
PaperPresentation

Generating Microcode Stimuli Using VCS Constraint Solver
Author(s): Rajat Bahl, Greg Tang [Advanced Micro Devices, Inc.], Padmaraj Ramachandran, Alexander Wakefield [Synopsys, Inc.]
PaperPresentation

MA3 User - XA
Simulation of the Global Clock Distribution Network in a High-Performance 40nm, 850-MHz Discrete GPU
Author(s): Tony Todesco, Victor Ma [Advanced Micro Devices, Inc.]
PaperPresentation

XA for Read Channel IC Design
Author(s): Gangqiang Zhang, Vineet Tiwari [STMicroelectronics], Felix Ruan [Synopsys, Inc.]
PaperPresentation

MA4 User - Design Methodologies
A Case Study – Hierarchical Design 2.0
Author(s): Vivek Rajan [Intel Corp.]
PaperPresentation

Designing Hierarchically Reusable Digital IPs Using DC-T/ICC Flow
Author(s): James Deng [Altera Corp.]
PaperPresentation

MA5 Tutorial & User - StarRC
User: Using StarRC Open Access Interface for Accurate and Productive Custom IC Design
Author(s): Mahesh Kondajji [Tabula, Inc.], Lalit Gajare [Synopsys, Inc.]
PaperPresentation

MB2 User - Verification with Magellan
A Reusable Magellan Formal Verification Environment
Author(s): Nantian Qian [Broadcom Corp.], Mandar Munishwar [Synopsys, Inc.]
PaperPresentation

RAM Models Verification Using Magellan
Author(s): Dan Smith, Amy Yen [NVIDIA Corp.], Mandar Munishwar [Synopsys, Inc.]
PaperPresentation

MB5 User - Signoff Correlation
Crosstalk Delay and Noise Correlation Flow between PrimeTime SI and HSPICE
Author(s): Tariq El Motassadeq [Dubai Circuit Design]
PaperPresentation

Power Correlation with Silicon - A PrimeTime PX Evaluation
Author(s): Steve Griffith [Aeroflex]
PaperPresentation

MC2 User - TLM and VMM
Exploiting the TLM-2 Features of VMM 1.2
Author(s): John Aynsley [Doulos]
PaperPresentation

Interoperable Testbenches using VMM TLM (Technical Committee Award Honorable Mention)
Author(s): Asif Jafri [Verilab Inc.], Nasib Naser [Synopsys, Inc.]
PaperPresentation

MC3 User - HSPICE
Constant-Current Threshold Voltage Extraction in HSPICE for Nanoscale CMOS Analog Design (1st Place - Best Paper, Best First-Time Presenter)
Author(s): Alvin Loke, Dru Cabler, Chad Lackey, Tin Tin Wee, Bruce Doyle [Advanced Micro Devices, Inc.], Zhi-Yuan Wu [GLOBALFOUNDRIES], Reza Moallemi [Synopsys, Inc.]
PaperPresentation

Multi-Threading & Multi-Processing HSPICE
Author(s): Tom Mahatdejkul [ARM Physical IP]
PaperPresentation

MC6 User & Tutorial - High Level Synthesis and Enabling Hierarchical Design Flow
User: Bridging the Gap between Advanced Image Processing and Hardware Design
Author(s): Richard Cagley [Toyon Research Corp.], Nicholas Hogasten [FLIR Commercial Vision Systems]
PaperPresentation

TA1 User - IC Validator and UPF
Design Rule Check Classification System with IC Validator for Sub-45nm Designs
Author(s): Pavel Rott [Intel Corp.]
PaperPresentation

Reusable UPF for Multi-Voltage Design & Handling Analog Macros in Power Subsystem (Technical Committee Award Honorable Mention)
Author(s): Krishna Vittala [Microchip Technology Inc.]
PaperPresentation

TA5 User - Scripts, Tricks and Setup
"There’s a better way to do it!" - Simple DC/PT Tricks That Can Change Your Life. (3rd Place - Best Paper)
Author(s): Paul Zimmer [Zimmer Design Systems]
PaperPresentation

Hold is Not Setup (Derate is Not OCV) (2nd Place - Best Paper)
Author(s): Gerard M Blair [LSI Corp.]
PaperPresentation

TB1 User - Design Rules and Methods I
High Performance Design Using Zroute on 65nm Process Technology
Author(s): Ramy Gamal [Dubai Circuit Design]
PaperPresentation

LeSa Lowers Leakage
Author(s): Bruce Zahn [LSI Corp.]
PaperPresentation

TB2 User - Verification Topics
Integrating eVCs in a VMM Testbench
Author(s): JL Gray [Verilab Inc.], Adiel Khan [Synopsys, Inc.]
PaperPresentation

QuickGrade: An Efficient Algorithm for Managing Coverage Grading in Complex Multicore Microprocessor Environments
Author(s): Michael Sanders, James Young [Advanced Micro Devices, Inc.], Paul Graykowski, Vernon Lee [Synopsys, Inc.]
PaperPresentation

TC1 User - Design Rules and Methods II
Accelerated Implementation TAT with In-Design Physical Verification
Author(s): Kyle Peavey [Texas Instruments], Sabbir Choudhury [Synopsys, Inc.]
PaperPresentation

Achieving Timing Closure Using Relative Placement Technology
Author(s): Krishna Kumar Gundavarapu [Cisco Systems, Inc.]
PaperPresentation

Clock Power Reduction-Analysis Metrics and Power Reduction Techniques (Technical Committee Award)
Author(s): Avishek Panigrahi, Arvind Parihar [MIPS Technologies, Inc.]
PaperPresentation

TC2 User - Design Project Management
Agile IC Development with Scrum
Author(s): Neil Johnson, Bryan Morris [XtremeEDA Corp.] (InSync)
PaperPresentation

Release Management: A Problem You Cannot Afford To Ignore (5 Steps to an Automated Release Flow)
Author(s): Jeffrey Wren [Paradigm Works]
PaperPresentation

TC3 Tutorial & User - Custom Design and HSPICE
User: Multi-Gigabit Serial Link Analysis using HSPICE and AMI Models
Author(s): Doug Burns, Barry Katz, Walter Katz, Mike Steinberger, Todd Westerhoff [SiSoft]
PaperPresentation

TC6 User - Implementation, Advanced Verification and Debug with FPGA-Based Rapid Prototyping Platforms
Automated Source Level Partitioning Flow for FPGA Rapid Prototyping with CHIPit
Author(s): Sunil Menon [Broadcom Corp.], David Castle [Synopsys, Inc.]
PaperPresentation Make File

SoC Emulation Methodology with Chipit Iridium
Author(s): German Fabila Garcia [Intel Corp.]
PaperPresentation

WA4 User - Advanced Test and Diagnostic Techniques for Large SOCs
A Core-Based ATPG Approach For a 5 Million Flop Design
Author(s): Charles Njinda [Cisco Systems, Inc.], Amy Mitby [Synopsys, Inc.]
PaperPresentation

Using Physical Layout Information to Improve the Effectiveness of Diagnosis Algorithms
Author(s): Vishal Mehta [NVIDIA Corp.]
PaperPresentation

Publication Only
For Publication Only
Test Protocol File (SPF) Mapping For Custom Scan Architecture
Author(s): Rao Lakamsani [STMicroelectronics, Inc.], Narasimha L Vadlamudi [Synopsys, Inc]
Paper

Tutorials
MA1 Tutorial
PrimeRail and IC Compiler: In-Design Rail Analysis for Faster Power Network Design Closure
Author(s): [Synopsys, Inc.]
Tutorial

MA5 Tutorial & User - StarRC
Tutorial: Design Signoff Beyond 45nm: Addressing Next-Generation Challenges with StarRC Extraction Solution
Author(s): Bari Biswas [Synopsys, Inc.]

MB1 Tutorial
In-Design Physical Verification for Faster Time to Tapeout
Author(s): Paul Friedberg, Ron Duncan [Synopsys, Inc.]
Tutorial

MB3 Tutorial
HSIMplus CircuitCheck for Low Power Transistor Level Error Detection
Author(s): [Synopsys, Inc.]
Tutorial

MB4 Tutorial
Galaxy RTL: Design Compiler Family 2010.03 Update
Author(s): [Synopsys, Inc.]
Tutorial

MB6 Tutorial
Tips and Tricks for FPGA Synthesis QoR, Debug, and Faster Turnaround Time
Author(s): Will Cummings [Synopsys, Inc.]
Tutorial

MC1 Tutorial
Vertically Optimized 32/28nm Solution for Mobile SoC Design
Author(s): Ana Hunter, Vice President of Foundry, [Samsung], Dr. Dipesh Patel, Vice President of Technology [ARM],

MC5 Tutorial
Using NanoTime for Improving Design Predictability and Productivity at Transistor-Level STA
Author(s): Chirag Patel, Sahil Bargal [Synopsys, Inc.]
Tutorial

MC6 User & Tutorial - High Level Synthesis and Enabling Hierarchical Design Flow
Tutorial: Enabling Hierarchical FPGA Design Flow
Author(s): Frederic Rivoallon [Xilinx, Inc.]
Tutorial

TA2 Tutorial
Low Power Verification
Author(s): [Synopsys, Inc.]
Tutorial

TA4 Tutorial
Increased Productivity and Higher Predictability with the Lynx Design System
Author(s): [Synopsys, Inc.]

TA7 Tutorial
A Thumbs Guide to Specifying and Understanding System Trade-Offs for Data Converter IP
Author(s): Navraj Nandra [Synopsys, Inc.]
Tutorial

TB3 Tutorial
StarRC Custom Extraction Tuned for High Performance CustomSim Simulation
Author(s): Satish Venigandla, Wen-Cheng Chang [Synopsys, Inc.]
Tutorial

TB4 Tutorial
Optimized Implementation Methodology for High Performance Low Power Processor Core at 40nm and Below
Author(s): Daniel Biset [Synopsys, Inc.]
Tutorial Video

TB5 Tutorial
Getting the Most from PrimeTime 2009.12
Author(s): [Synopsys, Inc.]
Tutorial

TB6 Tutorial
How to Leverage FPGA-Based Rapid Prototyping to Debug Elusive Hardware and HW/SW Bugs
Author(s): [Synopsys, Inc.]
Tutorial

TB7 Tutorial
Understanding PCI Express 3.0 and How to Implement the New Features
Author(s):
Tutorial

TC3 Tutorial & User - Custom Design and HSPICE
Tutorial: Custom Designer Demo including Presentation for Efficient Analog IP Migration
Author(s): Fredrik Ivarsson, Bob Lefferts [Synopsys, Inc.]
Tutorial

TC4 Tutorial
Low Power Multi-Voltage Design Implementation Methodology using the IEEE 1801 (UPF) Standard
Author(s): Jeffrey Lee [Synopsys, Inc.]
Tutorial

TC5 Tutorials
Faster Timing Convergence with PrimeTime ECO
Author(s): Jennifer Pyon [Synopsys, Inc.]
Tutorial

Galaxy Constraints Analyzer: Constraints Debugging Made Easy
Author(s): Lionel Corbet [Synopsys, Inc.]
Tutorial

TC7 Tutorials
The Fundamentals of Selecting High-Quality IP
Author(s): Ralph Morgan [Synopsys, Inc.]
Tutorial

Understanding HDMI 1.4 and How to Integrate the New HEAC Feature into SoCs
Author(s): Manmeet Walia [Synopsys, Inc.]
Tutorial

WA1 Tutorial
Energy Efficient Processor Implementation with Synopsys’ Eclypse Low Power Solution
Author(s): Alan Gibbons [Synopsys, Inc.]
Tutorial Webinar

WA5 Tutorial
In-System Calibration for High-Speed DDR Interface IP
Author(s): Dara Hurley [Synopsys, Inc.]
Tutorial

WA6 Tutorial
Increasing Verification Efficiency using Embedded Software Driven Verification
Author(s): Filip Thoen [Synopsys, Inc.]
Tutorial

WB1 Tutorials
Feasibility for IC Implementation
Author(s): Mehrang Razzaz [Synopsys, Inc.]
Tutorial

IC Compiler: Planning and Implementation of Large Hierarchical Designs
Author(s): Raghu S Parvataneni [Synopsys, Inc.]
Tutorial

WB2 Tutorial
VMM 1.2 for New Users
Author(s): [Synopsys, Inc.]
Tutorial

WB4 Tutorial
Test Automation Updates
Author(s): Adam Cron [Synopsys, Inc.]
Tutorial

WB5 Tutorial
Extreme Low-Power Datapath Design with DesignWare minPower Components
Author(s): Buvna Ayyagari-Sangamalli [Synopsys, Inc.]
Tutorial

WB6 Tutorial
The Best of Both Worlds – Combining Virtual and FPGA Prototyping for Verification and Embedded Software Development
Author(s): Frank Schirrmeister [Synopsys, Inc.]
Tutorial

WC1 Tutorial
IC Compiler 2010.03 Updates
Author(s): Simon Koval [Synopsys, Inc.]
Tutorial

WC2 Tutorial
VMM 1.2 for Current VMM Users
Author(s): [Synopsys, Inc.]
Tutorial

WC3 Tutorial
Best Practices in Infrastructure for EDA Tools
Author(s): Joe Fu, John Mincarelli, Glenn Newell, Venkata Ravella [Synopsys, Inc.]
Tutorial

WC5 Tutorial
Implementing USB 3.0 on your SoC: Soup to Nuts -- IP Instantiation to Compliance Testing
Author(s): Bob Lefferts [Synopsys, Inc.]
Tutorial

WC6 Tutorial
Extending Design Flows to the System-Level – How ESL Fits into Your Design Flow!
Author(s): Andy Haines [Synfora], Brett Cline [Forte], Steve Cox [Target Compiler], Chris Jones [Tensilica], Andrea Kroll [EDA Technologies], Bill Neiffert [Carbon Design Systems] Frank Schirrmeister [Synopsys, Inc.]
Tutorial

Panel Presentation
WA3 Panel
Cloud Computing and the Implications for EDA
Author(s): Vijay Bollapragada [Cisco Systems], Scott Clark [Broadcom Corp.], Jeff Barr [Amazon], Todd Martin [AppliedMicro], Kishore Singhal, Hasmukh Ranjan [Synopsys, Inc.]

WC4 Panel
Improving Yield: Is it a Design, Test or Fab Problem?
Author(s): Leah Clark [Broadcom Corp.], Luigi Capodieci [GLOBAL FOUNDRIES], Bruce Cory [NVIDIA], Manuel D'Abreu [SanDisk Corp.], Srikanth Venkataraman [Intel Corp.]

Speech
Guest Speaker
The Innovation Imperative: Defining a New Model for Semiconductor Manufacturing and Technology
Author(s): Doug Grose, Chief Executive Officer (CEO) - GLOBALFOUNDRIES

Guest Speaker
Collaborating for Success – A Historical Perspective
Author(s): Rick Cassidy, President - TSMC North America