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| User Papers and Presentations |
| MA1 - Using ICC to Close Timing |
Closing the Last Few Picoseconds Using IC Compiler: A 65nm Case Study
Author(s): Sarita Baswant, Umesh Patel [LSI Corp.] |
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Never Let Noise Delay Your Tape-Out
Author(s): Hongda Lu [AMD] |
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| MA2 - RTL Synthesis Design Techniques |
Fizzim – An Open-Source fsm Design Environment
Author(s): Paul Zimmer [Zimmer Design Services], Michael Zimmer [Zimmer Design Services / UCSB], Brian Zimmer [Zimmer Design Services / Zimmertech / UCD] |
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Getting Synchronous Resets Right! (Technical Committee Award)
Author(s): Noah Aklilu [Cisco Systems, Inc.], Anthony Redhead [XtremeEDA Corp.], Pervinder Trehan [Synopsys, Inc.] |
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| MA3 - AMS Sign Off |
PT-SI vs HSPICE Pushout and Glitch Correlation
Author(s): Louis Tseng [Raza Microelectronics] |
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Using NanoTime for Custom Digital Macros (Technical Committee Award Honorable Mention)
Author(s): Bingxiong Xu, Kevin Stiles [LSI Corp.], Cheung Lam, Louis Andrews [Synopsys] |
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| MB2 - Test - Getting the Most out of DFT MAX and TetraMAX |
DFT MAX for a Mixed-Signal Design - A Case Study
Author(s): Cory Ellinger [RFMD] |
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Getting to Production on First Silicon Using DFT MAX and TetraMAX
Author(s): Adrian Arozqueta, Christopher Ematrudo [PLX Technology] |
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Small Delay Defect Testing
Author(s): Roberto Mattiuzzo, Saverio Graniello [STMicroelectronics], Salvatore Talluto, Alfredo Conte, Adam Cron [Synopsys, Inc.] |
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| MB4 - Practical VMM |
Using VMM, DPI and TcL to Leverage Verification to Enable Early Testing, Emulation and Validation
Author(s): Samir Patel [LSI Corp.] |
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Verification of a New IP in Legacy SoC Design using SystemVerilog/VMM
Author(s): Asad Khan, Henry Angulo, David Kimble, Paul Howard [Texas Instruments], Jiri Prevratil, Praveen Devulapalli [Synopsys, Inc.] |
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Verification Patterns in Addition to RVM
Author(s): Carl Cavanagh, Christopher Sine, Lee Warner [Sun Microsystems, Inc.] |
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| MB6 - SoC Verification and Validation |
Incorporating SystemVerilog and SystemC to Verify Next-Generation Home-Networking Chip
Author(s): Ritero Chi, Ho-Ming Leung, Alex Li [Entropic Communications] |
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Migrating a Large-Scale Vera Testbench Infrastructure to SystemC and SystemVerilog - Risk Mitigation and Value Creation Strategies (1st Place - Best Paper, Best First-Time Presenter)
Author(s): Srinath Atluri, Nimalan Siva, Anant Sakharkar [Cisco Systems Inc.] |
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Virtual Reality for Modem Software Development - Enabling Pre-Silicon Software Development and Validation for 2.5G Wireless Communication
Author(s): Alain Pegatoquet [Texas Instruments], Filip Thoen, Denis Paterson [Synopsys, Inc.] |
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| MB7 - AMS |
Memory Bitmap Verification Using ESP-CV
Author(s): Jijun Chen [ARM, Ltd.] |
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| MC4 - Formal Verification with Magellan |
End-to-End Verification of an Arbiter with Magellan
Author(s): Hari Ganesan, Devin Volpe [Sun Microsystems] |
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Verifying MIPS Designs using Magellan
Author(s): Ali Habibi, Jithendra Madala [MIPS Technologies, Inc.], Mandar Munishwar, Haihui Chen [Synopsys, Inc.] |
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| MC5 - Verification IP and VMM: Benefits and Real World Experiences |
Using Verification IP and VMM Applications to Jumpstart Verification of an AXI Subsystem
Author(s): John Dickol [MediaTek Wireless, Inc.] |
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Verification IP Reuse for Complex Networking ASICs Using a Hybrid SystemVerilog/ SystemC Environment
Author(s): Ben Chen, Srinath Atluri, Harry King [Cisco Systems, Inc.], Shankar Hemmady [Synopsys, Inc.] |
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| MC7 - AMS Simulation |
Power Measurement Flow for ARM Memory Compilers Using Synopsys HSIMplus
Author(s): Satinderjit Singh [ARM, Ltd.] |
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| TA1 - Placement and Layout Optimization Using ICC |
A Hierarchical Design Flow for Floorplan and Layout Optimization: A Case Study
Author(s): Santiago Fernandez-Gomez, Monica Nofal [Apple, Inc.] |
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Placement Issues in ICC with Impact on Power
Author(s): Bharat Krishna [Intel Corp.], Nancy Khoury [Syracuse University] |
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| TA2 - Low Power Design |
Design for State Retention: Strategies and Case Studies (Technical Committee Award Honorable Mention)
Author(s): David Flynn [ARM, Ltd], Alan Gibbons [Synopsys] |
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Power Analysis Methodology: From Spreadsheet to Sign Off
Author(s): George Cuan, Dinesh Patel [Cisco Systems, Inc.] |
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Power-Aware FPGA Design
Author(s): Hichem Belhadj, Vishal Aggrawal, Amal Zerrouki, Ajay Pradhan [Actel Corp.] |
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| TA5 - Design Using IP |
Methodology for Designing a Power Control Circuit for IP Block
Author(s): Shailja Garg, Sanjay K Sancheti, Anup Nayak [Cypress Semiconductor] |
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| TB2 - Design Flows |
Closing the Gap Between Synthesis and P&R
Author(s): Madhusudan Kalluri, Kapil Gaba [LSI Corp.] |
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Structured Methods for Delay, Power Tuning and Variation: A Case Study Comparing Relative Placement and Clock Mesh to Standard Placement and Standard Clock Trees on a 90 Nanometer Technology Node Using a Multi-Media Block of ARM's Cortex-A8 Microprocessor
Author(s): Haroon Gauhar, Ashutosh Mujumdar, Stephanie Miller, Dermott O'Driscoll [ARM, Ltd.], Yuichi Kawahara, Mallik Devulapalli, Jason Binney, Tom Chau [Synopsys] |
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| TB4 - VMM, RAL, AOP: What Does It All Mean? |
A Fully Reusable Register/Memory Access Solution using VMM RAL
Author(s): Paul Lungu, Bo Zhu [Nortel] |
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Techniques for Selective Reuse of Verification Components in Hierarchical Verification of Large Designs
Author(s): Tony Tsai [Cisco Systems, Inc.] |
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| TC2- Lower Power Verification |
Challenges of Multi-Voltage Verification on a Complex Low-Power Design
Author(s): Sudhakar Ram [NVIDIA], Ajay Krishna, Prapanna Tiwari [Synopsys, Inc.] |
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Low Power Rule Checking Using Leda
Author(s): Shailja Garg, Jason Ferrell, Sanjay K Sancheti, Parthasarathy Narasimhan, Anup Nayak [Cypress Semiconductor] |
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| TC3 - Improving Sign Off Accuracy |
CCS and NLDM Timing Characterization and Correlation with Liberty-NCX
Author(s): Ronald Kalim [Cypress Semiconductor], Pat Donahue [Synopsys] |
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Fast and Efficient Power Mesh Resistance Calculation Pre-Tapeout Check to Prevent Damaging Circuits During ESD Event
Author(s): Ashish Rajput, Joe Louis-Chandran [Rambus Chip Technology Inc.] |
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| TC4 - SystemVerilog Interfacing & Simulation Coverage |
Are We There Yet? (2nd Place - Best Paper)
Author(s): Nancy Pratt [IBM], Dwight Eddy [Synopsys, Inc.] |
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Bridging the Application and Design Gap: Utilization of the GDB Proxy Protocol for Remote Control of a VCS Simulation
Author(s): Kelly D Larson [MediaTek Wireless, Inc.] |
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| TC6 - Hercules |
Addressing Differential Antenna's In Low Voltage SOI Processes Using Hercules
Author(s): Barry O'Connell, Nam Nguyen, Pilar Hsue [National Semiconductor], Lalit Gajare, Elango Velayutham [Synopsys] |
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| WA4 - VMM in Practice |
OpenVera/RVM to SystemVerilog/VMM Conversion: How to Avoid 'Death By a Thousand Cuts' (3rd Place - Best Paper)
Author(s): Venkata Chintapalli, Dan Steinberg [Integrated Device Technology] |
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Randomized Testbench Development, a Case Study in USB
Author(s): Jason Remple [Broadcom Corp.], Denis Bussaglia, Frederic Krampac [Synopsys, Inc.] |