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| User Papers and Presentations |
| For Publication Only |
An EM Verification Flow for Large AMS Designs with StarRCXT and HSIM
Author(s): Wei-Si Jiang [National Semiconductor Corp.] |
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| MA1 - ICC for Floorplan / Placement |
A Systematic Approach to Automated Floorplan Exploration in ICC-DP (65nm)
Author(s): Umesh Patel, Jeff Shi [Agere Systems], Shubharthi Datta [Synopsys, Inc.] |
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Efficient Physical DataPath Specification: Streaming Relative Placement
Author(s): Jeff Dunham, Anand Arunachalam [Synopsys, Inc.] |
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Physical Synthesis for Microprocessor Design
Author(s): Harry H. Yu, Raj Varada [Intel Corp.] |
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| MA2 - DFT for SoC |
Core Based Test using Scan Compression and Core Isolation
Author(s): Paul Policke [QUALCOMM], Sandeep Kaushik [Synopsys, Inc.] |
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Hybrid Test Methodology for a Multi-Million Gate Design
Author(s): Leah Clark, Amar Guettaf [Broadcom Corp.] |
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| MA3 - Delivering DFM - Early, Accurately, Efficiently |
Accelerating High Yield Design with Implementation-Stage Lithography Correction
Author(s): Atsuhiko Ikeuchi, Hiroaki Suzuki, Suigen Kyoh, Kyoko Izuha [Toshiba Corp.], Gerard T. Luk-Pat, Alexander Miloslavsky, Frank Tseng, Linni Wen [Synopsys, Inc.] |
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Accurate Lithography Analysis for Yield Prediction
Author(s): Greg Yeric, Babak Hatamian, Rahul Kapoor [Synopsys, Inc.] |
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Smart Density Checking
Author(s): Selvaraj Henry [Intel Corp.] |
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| MA4 - Low Power Methodologies |
Analyzing Power Integrity on Power Gated Designs
Author(s): Anil Gundurao and Sanjay Sancheti [Cypress Semiconductor] |
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Early Exploration of Multiple Voltage Domains and Activity-driven Clock-gating
Author(s): Udupi Harisharan [Cisco Systems Inc.] |
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Physical and Silicon Measures of Low Power Clock Gating Success: An Apple to Apple Case Study
Author(s): Khem C Pokhrel [Intel Corp.] |
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| MA6 - Advanced HSIM Applications in Various Design Flows |
Experience of SRAM Design in 65nm/45nm Process
Author(s): Derek Tao, Hans Liao [TSMC] |
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Integration of HSIM-NCverilog and C-code as part of Micron's Simulation Methodology
Author(s): Uday Chandrasekhar [Micron Technology Inc.] |
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Simulation Success with HSIM in Nanometer Design
Author(s): Arvind Vidyarthi [Altera Corp.], Reynaldo Hernandez [Synopsys, Inc.] |
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| MA7 - Virtual Platforms and Transaction Level Modeling |
System Level Verification: A Case Analysis with Virtio
Author(s): Kalyan Chakravadhanula [Texas Instruments] |
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| MB1 - Digital Design |
Advantages of Driving DDR Interface Logic at 2x the DDR Clock Versus 1x the DDR Clock
Author(s): Pete Thoeming [Thomson Silicon Components], Ken Umino [Synopsys, Inc.] |
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Design of a 1GHz DSP using IC Compiler
Author(s): Anthony Hill, Mike Gill, Arjun Rajagopal, Todd Beck [Texas Instruments] |
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| MB4 - Low Power Design for Higher Performance |
Decoupling Capacitance Estimation, Implementation, and Verification: A Practical Approach for Deep Submicron SoCs
Author(s): David Stringfellow, John Pedicone [Synopsys, Inc.] |
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Increasing Designer Productivity with the ARM Cortex-A8 Processor's Rapidly Deployable Synthesizable Implementation
Author(s): Dermot O'Driscoll [ARM Ltd.] |
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| MB5 - Practical SystemVerilog I |
Gotcha Again - More Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know (2nd Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Stuart Sutherland [Sutherland HDL, Inc.], Don Mills [LCDM Engineering], Chris Spear [Synopsys, Inc.] |
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Implementation of an AHB Bus Subsystem with SystemVerilog (Technical Committee Award)
Author(s): Eliseu C Filho [Starport Systems, Inc.], Jim Maryoung [Synopsys, Inc.] |
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| MC5 - Practical SystemVerilog II |
Using SystemVerilog to Ensure a Quality Transition to Randomized Tests
Author(s): John Stubban [Micron Technology] |
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| MC6 - HSIM Static Power Net Resistance Analysis |
HSIM SPRES: Efficient Powergrid Analysis for Voltage-Drop Problems
Author(s): Huijuan Wang [SanDisk Corp.], Min Guo [Synopsys, Inc.] |
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| TA1 - Transitioning from Astro to IC Compiler |
ASIC Predictability with Semi-Custom Performance... Is IC-Compiler the Holy Grail?
Author(s): Philip Watson [ARM Inc.], Stephen Edgeworth [Synopsys, Inc.] |
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Migration from Astro to ICC & Achieving Design Closure Using Core Commands
Author(s): Sunil Malkani [Broadcom Corp.], Radhika Shankar [Synopsys, Inc.] |
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Usage of ICC for Concurrent Multi-corner Optimization Technology at AMD
Author(s): Muthukumaravelu Velayoudame, Rainer Mann [AMD] |
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| TA4 - Signoff |
An Efficient Timing Method for Checking Asynchronous Gray Code Transfers
Author(s): Eric Masson [NVIDIA Corp.] |
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Moving to NanoTime, The Next Generation Transistor Level STA
Author(s): Timothy Raap [Cray Inc.] |
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Where Have all the Phases Gone? Using Multiclock Propagation in PrimeTime (1st Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Paul Zimmer [Zimmer Design Systems] |
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| TA6 - Nanosim-VCS Co-Simulation Methodology Flow |
Methodology for Co-Simulation of Mixed-Signal IP
Author(s): Jeff McNeal, David A Yokoyama-Martin [Synopsys, Inc.] |
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| TA7 - Reusable IP and Methodologies |
Automated Tool to Generate Quality Synopsys IP Views
Author(s): Ronald Kalim, Geetha Chigullapalli [Cypress Semiconductor], Joe Varghese, Alpesh Kothari [Synopsys, Inc.] |
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How to Verify and Integrate Mixed Signal Third-Party IP (Best First-Time Presenter)
Author(s): Steven M Waldstein [Tundra Semiconductor], Navraj S Nandra [Synopsys, Inc.] |
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Physical Design and Timing Challenges of a Serial PHY
Author(s): Steve Everley [Everley Consulting, LLC], Ken Umino, Jason Upton, Ross Segelken, John Stonick [Synopsys, Inc.] |
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| TB4 - Advanced SI & Variation Aware Signoff |
An LLC Timing Sign-Off Model to Cover On-Chip Process Variation
Author(s): Jerry Hong, J D Pan, Peter Pong, Sammy Lee, Simon Ku [Faraday Technology Corp.] |
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Composite Current Source (CCS) Noise Characterization for Standard Cell IP at ARM
Author(s): Neeraj Dogra, Kevin Bui [ARM Inc.] |
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Variation-aware STA Evaluation at QUALCOMM
Author(s): Xin Bao, Alon Ben-Efraim, Ran Lu [QUALCOMM], Elisabeth Moseley [Synopsys, Inc.] |
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| TB5 - VMM Environment |
Deploying SVTB, VMM and AHB VIP on a New Design
Author(s): Junfeng Wang, YC Wong [Broadcom Corp.], Amir Nilipour, Susan Sien [Synopsys, Inc.] |
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Generating VMM Compliant Environments- A Template Based Approach
Author(s): Dr. Ambar Sarkar [Paradigm Works, Inc.] |
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System Testbench Integration and Reference Verification Methodology: Problems and Solutions
Author(s): David Shleifman [Tundra Semiconductor] |
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| TC2 - DFTMax |
DFTMax Clinic for Low Power Design
Author(s): Johnie Au [Cypress Semiconductor] |
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Moving to DFTC / DFTMax Flow at QUALCOMM
Author(s): Tsvetomir Petrov, Xiaoyun Sun, Philip Schremmer, Shivakumar Swaminathan, Hyung Lee [QUALCOMM], Paul Micheletti [Synopsys, Inc.] |
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| TC5 - VMM Best Practices |
Getting the Most Out of Functional Coverage - Tips and Techniques
Author(s): Stephen J. D'Onofrio, Ambar Sarkar [Paradigm Works] |
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Stepping Up to Scenarios in VMM
Author(s): Pierre Girodias, Hans van der Schoot, Amre Sultan [XtremeEDA Corp.] |
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| TC6 - HSPICE Advanced SI and Jitter Analysis |
PLL Random Jitter Estimation Using Different VCO Phase Noise Simulation Methodologies
Author(s): Metha Jeeradit, Yohan Frans, Reza Navid, Bruno Garlepp [Rambus Inc.] |
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System Level Timing Closure Using HSPICE
Author(s): Todd Westerhoff, Barry Katz [SiSoft] |
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| WA2 - DC Topographical / Equivalence Checking |
Don't Panic! What to do when Formality Doesn't Give You the "VERIFICATION SUCCEEDED" Message on the First Try. (3rd Place - Best Paper)
Author(s): Leah Clark [Broadcom Corp.], Matt Dittrich [Synopsys, Inc] |
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Evaluation of DC-Topographical
Author(s): Branimir Malnar, Goran Zelic, Santana Lewis, Raghu Raman [Intel Corp.], Craig Maiman [Synopsys, Inc.] |
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Will DCT Really Let Me Get Rid of Wire Load Models? Analysis of a DCT Qualification Effort
Author(s): Chris Kiegle, Maurice Kinney, Chang Suh [IBM], Ray Yock [Synopsys, Inc.] |
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| WA5 - High Level Verification |
Adopting Hybrid-Formal Methodology for Arbiter Verification
Author(s): Jing Li, Chris Wattana, Mandar Munishwar [Broadcom Corp] |
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Applying CRV to Microprocessor Verification
Author(s): Jason C Chen [Synopsys, Inc.] |
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Verifying Cache Structures with Magellan
Author(s): Thomas J Thatcher [Sun Microsystems] |