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| User Papers and Presentations |
| MA2 - SystemVerilog Testbenches |
Verifying a Networking ASIC using a SystemC Reference Model and a SystemVerilog Testbench
Author(s): Amit Malhotra [Cisco Systems], Angshuman Saha, Sanjaya Sharma [Synopsys, Inc.] |
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| MA3 - Timing Verification Methodologies |
A Bottom up Constraint Methodology for use with Hierarchical Designs
Author(s): Noah Aklilu [Cisco Systems] |
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The Last Mile of Physical Design: Timing Closure Loops Between Implementation and Signoff
Author(s): Raghavendra Dasegowda, Paras Gupta [Qualcomm, Inc.] |
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| MA4 - Design for Test |
Improving Test Quality while Reducing Test Cost using DFT Compiler Max and the DSM Features in TetraMAX ATPG
Author(s): Amar Guettaf [Broadcom Corp.] |
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Squeezing Test Pattern and Pin Counts using DBIST on a 1.5M Gate Device for a Low Cost Test Solution (Technical Committee Award Honorable Mention)
Author(s): Pradeep Atur [Cypress Semiconductor], Paul Micheletti [Synopsys, Inc.] |
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| MA5 - DFM with Hercules |
Correlating Manufacturing Results and Design Architecture Tradeoffs with Hercules
Author(s): Pallab Chatterjee, Mike Gentry [SiliconMap, LLC] |
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Using Hercules as a Yield Enhancement Tool for Nanometer Designs
Author(s): Huijuan Wang, Michael Wang, Albert Wong, Norman Louie [SanDisk Corp.] |
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| TA1 - Backend Flows |
Efficient Design Flow for Small Digital, Large Analog Mixed Signal Designs
Author(s): Stephen Lin, Venkat Kowkutla [Texas Instruments Inc.] |
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Hierarchical Astro-Rail Analysis of a One-billion-transistor, Full-custom Design
Author(s): Jia-Lih Chen, Thierry Lemeunier, Dustin Do, Sudheesh Madhavan, Yaron Kretchmer [Altera Corp.] |
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| TA3 - Vendor Session: Enhancing Productivity with Third-Party Tools |
Electronic System Level (ESL) Debug -- Trends, Requirements, and Technology
Author(s): Bindesh Patel, Harish Poojary [Novas Software] |
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Power Optimization in FPGA Designs
Author(s): Mouzam Khan [Altera Corp.] |
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| TA6 - IP |
High Speed Serial Interconnects - What to Look for When Selecting an IP Vendor
Author(s): Boris Litinsky [RF Microdevices], Navraj Nandra [Synopsys, Inc.] |
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Integrating DesignWare Digital IP Core for PCI Express into Agere's ET1310 Gigabit Ethernet Controller
Author(s): Fadi Saibi [Agere Systems], Jing-fan Zhang [Synopsys, Inc.] |
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| TB2 - Verification I |
Creating a VMM Compliant Verification Plan
Author(s): Ambar Sarkar [Paradigm Works] |
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VMMing a SystemVerilog Testbench by Example (Technical Committee Award)
Author(s): Ben Cohen [VhdlCohen Publishing], Srinivasan Venkataramanan, Ajeetha Kumari [Independent] |
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| TB3 - Experiments and Experiences with SystemVerilog and SystemC |
A SystemVerilog Class Template for Finite State Machine Design
Author(s): Swapnajit Mitra [Project VeriPage Inc.] |
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An Integrated SystemC/Verilog RTL Simulation Infrastructure for Co-simulation of ESL Models
Author(s): David Goldberg [Synfora Inc.] |
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| TC2 - RVM |
Getting off the Ground when Creating an RVM Testbench
Author(s): Rich Musacchio, Ning Guo [Paradigm Works Corp.] |
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Integrating System Models in an RVM Leveraged Environment
Author(s): Anand Acharya [Qualcomm], Shaun Evans [Synopsys, Inc.] |
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| TC3 - Design Transformation Pitfalls Revealed |
Physical Layer Verification for PCI Express (3rd Place - Best Paper)
Author(s): Dan Steinberg [Integrated Device Technology] |
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| TD3 - Getting the Most out of Magellan - Using SVA Constraints and Setup Tricks |
How to Get your REALLY Difficult Properties Proven
Author(s): Thomas Thatcher [Sun Microsystems] |
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SystemVerilog Constraints for Assertion-based Formal Verification
Author(s): Hanif Perwad [SGI], Mandar Munishwar [Synopsys, Inc.] |
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| WA1 - Floorplanning and Physical Design |
1.2 - 1.5+ M Instances Flat Design for 0.13um Process
Author(s): Steve Doan, Koshi Matsushita, Chien-yeh Wu, Srini Burugu [Synopsys, Inc.] |
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Floorplanning a Multi-Million Instance Design with JupiterXT's Virtual Flat Methodology
Author(s): Xin Chang, Jessica Zhang [Via/S3 Graphics], Antonio Dimalanta [Synopsys, Inc.] |
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| WA2 - Assertions Based Verification |
Assertion Based Checkers for Serial Protocols: Special Considerations
Author(s): Monika Talwar, Jitendra Puri [nSys Design Systems Pvt Ltd.], Soumen Basak [Synopsys, Inc.] |
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PSL |=> SVA: A Case Study in The Use of Assertions, and The Power of SVA (Technical Committee Award Honorable Mention)
Author(s): Al Czamara [LOA Technology] |
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SystemVerilog Assertions are for Design Engineers Too! (2nd Place - Best Paper)
Author(s): Stuart Sutherland [Sutherland HDL, Inc.], Don Mills [LCDM Engineering] |
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| WA3 - Techniques for Solving Unique Design Challenges |
Automated FFT RTL Creation using Verilog with Matlab and Perl
Author(s): John Kuhns, Cole O'Berry, Richard Hayden [Synopsys, Inc.] |
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Automated FFT RTL Creation using Verilog with Matlab and Perl
Author(s): John Kuhns, Cole O'Berry, Richard Hayden [Synopsys, Inc.] |
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Oh, Synchronous Reset!
Author(s): Linming Jin [Brocade Communication Systems], Leo Butler [3Leaf Networks] |
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Solving Timing Convergence Problems in High Performance Processor Designs
Author(s): Zia Khan, Imtiaz Hussain,Nelson Chan [Intel Corp.] |
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| WA4 - Verification II |
Digital Simulation of Multi-Power Well Designs using PLI
Author(s): Uri Segal [SMSC] |
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Leda Use in Industry: Design Quality Improvements and Proprietary System Integration
Author(s): Scott Vento [IBM Systems and Technology Group], Raymond Yock [Synopsys, Inc.] |
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Using SystemVerilog Testbench for High Level Behavioral Modeling of a SIMD Processor Design (Best First-Time Presenter)
Author(s): Shankar Govindaraju, Jayanto Minocha, Kevin Rich, David Dobrikin [Transmeta Corp.] |
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| WA5 - Libraries and Modeling |
Automatic MilkyWay Technology File Generation
Author(s): Ronald Kalim, David John [Cypress Semiconductor], Sridhar Panchapakesan, Liang Xu [Synopsys, Inc.] |
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Basic Characterization Analog IP
Author(s): Peter Chen, Harrison Liu, Peter Pong, Jim Wang, K.C. Wu, Alvin Chen, David Chen [Faraday Technology Corp.] |
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Timing Sign-off using CCS Libraries at QUALCOMM
Author(s): Xin Bao, Khusro Sajid [Qualcomm, Inc.], Elisabeth Moseley [Synopsys, Inc.] |
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| WA6 - Advanced Timing Analysis |
An Automated Methodology for Systematic Analysis of the Timing Impact of Cells with Tied Input Pins
Author(s): Vishwas Rao, Stephanie Lam Alter [Agere Systems] |
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Critical Paths Verification and Debugging with PrimeTime Advanced Features (1st Place - Best Paper)
Author(s): Wei-Si Jiang [National Semiconductor] |
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Getting DDRs 'write' - the 1x Output Circuit Revisited (1st Place - Best Paper)
Author(s): Paul Zimmer [Zimmer Design Services] |