SNUG San Jose 2004 Proceedings

2011|2010
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User Papers and Presentations
MA1 - Next Step in Functional Verification and Simulation
Hardware/Software Tradeoffs in SystemC
Author(s): Deepesh Man Shakya, Richard Gallery [Institute of Technology, Blanchardstown]
PaperPresentation

Improving Fault Tolerance for Synopsys VCS Jobs on Platform LSF Compute Farms through Checkpointing
Author(s): Arend Dittmer [Platform Computing]
PaperPresentation

Zero Defects! Verifying a Complex PAD Ring Using OpenVera Assertions
Author(s): Laucresha Salmon [Motorola, Inc.], Hemendra Talesara [Synopsys Inc.]
PaperPresentation

MA2 - Timing Closure
System Level STA Methodology with DDR
Author(s): Robin Ko [LSI Logic]
PaperPresentation

Timing Convergence and Robust Clock System Design for a 10M Gate SoC
Author(s): Rune Jensen [ReShape Inc.]
PaperPresentation

MA3 - Compile and Data Management Strategies
Automated (Sub) Chip Synthesis - Using ACS on the Subchip Level (3rd Place - Best Paper)
Author(s): Paul Zimmer [Zimmer Design Services]
PaperPresentation

Project Delivery System - Managing Deliverables Efficiently
Author(s): Ganesh Babu Chelliah [Texas Instruments Inc.]
PaperPresentation

TC1 - Deep Sub-Micron Test Methodologies
Advanced Scan Debug Techniques using TetraMAX ATPG and Teseda Personal Tester
Author(s): Amar Guettaf [Broadcom Corp.], Geir Eide [Teseda Corp]
PaperPresentation

At-Speed Design For Test of Deep Sub-Micron ASICS
Author(s): Christopher Dolan [Calix Networks]
PaperPresentation

Power Compiler and DFT Compiler: Making them work together -- lessons learned
Author(s): Henry George Berkley [ASIC Wizard Group]
PaperPresentation

To BIST or not to BIST: that is the question.
Author(s): Amar Guettaf [Broadcom Corp.], Robert Moussavi [Synopsys Inc.]
PaperPresentation

TC2 - Design and Verification Challenges
All My X's Come From Texas. Not!!
Author(s): Matt Weber, Jason Pecor [Silicon Logic Engineering]
PaperPresentation

Being Assertive with your X (SystemVerilog Assertions for Dummies)
Author(s): Don Mills [LCDM Engineering]
PaperPresentation

SystemVerilog Tips & Techniques for New and Existing Design Flows
Author(s): Clifford Cummings [Sunburst Design, Inc]
PaperPresentation

The Verilog PLI is Dead (maybe) -- Long Live the SystemVerilog DPI!
Author(s): Stuart Sutherland [Sutherland HDL, Inc.]
PaperPresentation

TC3 - FPGA Prototyping and Synthesis Techniques
MATLAB to Silicon: The Other Behavioral Language.
Author(s): Michael Bohm [AccelChip]
PaperPresentation

Prototyping Wireless Designs Using Synopsys FPGA Synthesis
Author(s): Leo Borromeo [Zyray Wireless Inc.]
PaperPresentation

Using FPGAs to Prototype Wireless Systems
Author(s): Han Nuon [Qualcomm]
PaperPresentation

TC4 - Physical Design Techniques - Automation, Visualization, and Integration
A Picture is Worth a Thousand Words: Tips and Techniques for Graphical Debug in Physical Design
Author(s): Pete Churchill [EdgeRate Consulting]
PaperPresentation

AstroRail: Tips, Tricks and Gotchas
Author(s): Ersin Beyret [ReShape Inc.]
PaperPresentation

Clock Tree Optimization: An Algorithm and a Methodology
Author(s): Anis Jarrar, Colin MacDonald, Bryan Weston [Motorola Inc.]
PaperPresentation

Scheme: Tips and Tricks
Author(s): Venu Sanaka, Malcolm White [Corrent Corp.]
PaperPresentation

SCRIPTS: A Picture is Worth a Thousand Words: Tips and Techniques for Graphical Debug in Physical Design
Author(s): Pete Churchill [EdgeRate Consulting]

TD2 - Efficient Verification Methodologies
Creating HyperTransport Verification IP Using Vera
Author(s): Vijayalakshmi Pethachi, Jyotsna Menon, GuruPrasad Karaje [GDA Technologies], Ramnath S. [Xambala]
PaperPresentation

Formal Verification of a Packet Reordering Scheme Based on the HyperTransport Protocol
Author(s): John A. Thomson [Worcester Polytechnic Institute]
PaperPresentation

TD3 - Transistor Level Design
Library Modeling for Effective Leakage Management
Author(s): Rob Aitken, Scott Bordelon, Duane Champoux, Jim Shiffer [Artisan Components]
PaperPresentation

Optimizing Memory Power/Performance Tradeoffs
Author(s): Rob Aitken, Ravi Bhatia [Artisan Components]
PaperPresentation

TD4 - Power Management and Low Power Design
Area and Power Recovery without Sacrificing Timing
Author(s): Zia Khan, Imtiaz Hussain, Jackson Lee, Nai-Ying Chan [Intel Corp.]
PaperPresentation

Optimization Of Leakage Power With PrimeTime (2nd Place - Best Paper)
Author(s): Krzysztof Kozminski [National Semiconductor Corp.]
PaperPresentation

WA1 - Signal Integrity
A Practical Approach to the Full-chip Dynamic IR Drop Verification with Synopsys Tools
Author(s): Wei Si Jiang, Myung Kong [National Semiconductor Corp.]
PaperPresentation

Addressing CrossTalk - Achieving Timing Closure
Author(s): Colin MacDonald, Anis Jarrar [Motorola Inc.]
PaperPresentation

PrimeTime SI Noise analysis
Author(s): Elisabeth Moseley [Synopsys Inc.], Ken Wong [Conexant Systems]
PaperPresentation

WA2 - IP
Power Management Techniques for Soft IP
Author(s): Peter Greenhalgh [ARM]
PaperPresentation

Technology Abstraction Eases Silicon Intellectual Property Portability
Author(s): Jason Pecor, Matt Weber [Silicon Logic Engineering]
PaperPresentation

WA3 - Systemizing the EDA System
ASIC/SOC Implementation Stations - Constructing Design Flows
Author(s): Daniel Tang [Exar Corporation]
PaperPresentation

Multi-Mode Constraint Management Methodology
Author(s): Baris Aksoy [Calix]
PaperPresentation

The Human ECO Compiler (1st Place - Best Paper)
Author(s): Steve Golson [Trilobyte Systems]
PaperPresentation

Tutorials
MB1
Recommended Astro Methodology
Author(s):
Tutorial

MB2/MC2
Synthesis Highlights in DC 2004
Author(s):
Tutorial

MB3
Signal Integrity Flow
Author(s):
Tutorial

MC1
Using JupiterXT's Virtual Flat Flow for Quicker Design Implementation in Astro
Author(s):
Tutorial

MC3
Design and Coding Techniques for High Performance Flows
Author(s):
Tutorial

MC6
Industry Trends and Customer Applications in Mixed-Signal Design
Author(s):
Tutorial

TA1
Getting More Performance from Hercules' Sub-nanometer Complex Check Sequences
Author(s):
Tutorial

TA3/TB3
PrimeTime & PrimeTime SI Release Updates & Crosstalk Analysis
Author(s):
Tutorial

TA4
Power Management Techniques for Design Closure
Author(s):
Tutorial

TB1
Design for Manufacturing: 90-nm and beyond
Author(s):
Tutorial

TB5
Design Once - Unified Flow for ASIC and FPGA Design
Author(s):
Tutorial

WB1/WC1
Power Integrity/Reliability Analysis
Author(s):
Tutorial

WB2
Physical Compiler Highlights in 2003.12
Author(s):
Tutorial

WB4
Design for Verification: Dynamic and Static Methods in Functional Verification
Author(s):
Tutorial

WB5/WC5
Galaxy Design Platform's Test Solutions: DFT Compiler, SoCBIST and TetraMAX 2003.12 Updates
Author(s):
Tutorial

WC2
Using SystemVerilog for Design
Author(s):
Tutorial

WC4
A Complete Equivalence Checking Solution For Full Chip SOC Designs
Author(s):
Tutorial