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| User Papers and Presentations |
| MA1 - Next Step in Functional Verification and Simulation |
Hardware/Software Tradeoffs in SystemC
Author(s): Deepesh Man Shakya, Richard Gallery [Institute of Technology, Blanchardstown] |
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Improving Fault Tolerance for Synopsys VCS Jobs on Platform LSF Compute Farms through Checkpointing
Author(s): Arend Dittmer [Platform Computing] |
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Zero Defects! Verifying a Complex PAD Ring Using OpenVera Assertions
Author(s): Laucresha Salmon [Motorola, Inc.], Hemendra Talesara [Synopsys Inc.] |
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| MA2 - Timing Closure |
System Level STA Methodology with DDR
Author(s): Robin Ko [LSI Logic] |
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Timing Convergence and Robust Clock System Design for a 10M Gate SoC
Author(s): Rune Jensen [ReShape Inc.] |
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| MA3 - Compile and Data Management Strategies |
Automated (Sub) Chip Synthesis - Using ACS on the Subchip Level (3rd Place - Best Paper)
Author(s): Paul Zimmer [Zimmer Design Services] |
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Project Delivery System - Managing Deliverables Efficiently
Author(s): Ganesh Babu Chelliah [Texas Instruments Inc.] |
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| TC1 - Deep Sub-Micron Test Methodologies |
Advanced Scan Debug Techniques using TetraMAX ATPG and Teseda Personal Tester
Author(s): Amar Guettaf [Broadcom Corp.], Geir Eide [Teseda Corp] |
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At-Speed Design For Test of Deep Sub-Micron ASICS
Author(s): Christopher Dolan [Calix Networks] |
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Power Compiler and DFT Compiler: Making them work together -- lessons learned
Author(s): Henry George Berkley [ASIC Wizard Group] |
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To BIST or not to BIST: that is the question.
Author(s): Amar Guettaf [Broadcom Corp.], Robert Moussavi [Synopsys Inc.] |
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| TC2 - Design and Verification Challenges |
All My X's Come From Texas. Not!!
Author(s): Matt Weber, Jason Pecor [Silicon Logic Engineering] |
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Being Assertive with your X (SystemVerilog Assertions for Dummies)
Author(s): Don Mills [LCDM Engineering] |
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SystemVerilog Tips & Techniques for New and Existing Design Flows
Author(s): Clifford Cummings [Sunburst Design, Inc] |
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The Verilog PLI is Dead (maybe) -- Long Live the SystemVerilog DPI!
Author(s): Stuart Sutherland [Sutherland HDL, Inc.] |
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| TC3 - FPGA Prototyping and Synthesis Techniques |
MATLAB to Silicon: The Other Behavioral Language.
Author(s): Michael Bohm [AccelChip] |
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Prototyping Wireless Designs Using Synopsys FPGA Synthesis
Author(s): Leo Borromeo [Zyray Wireless Inc.] |
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Using FPGAs to Prototype Wireless Systems
Author(s): Han Nuon [Qualcomm] |
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| TC4 - Physical Design Techniques - Automation, Visualization, and Integration |
A Picture is Worth a Thousand Words: Tips and Techniques for Graphical Debug in Physical Design
Author(s): Pete Churchill [EdgeRate Consulting] |
|
AstroRail: Tips, Tricks and Gotchas
Author(s): Ersin Beyret [ReShape Inc.] |
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Clock Tree Optimization: An Algorithm and a Methodology
Author(s): Anis Jarrar, Colin MacDonald, Bryan Weston [Motorola Inc.] |
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Scheme: Tips and Tricks
Author(s): Venu Sanaka, Malcolm White [Corrent Corp.] |
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SCRIPTS: A Picture is Worth a Thousand Words: Tips and Techniques for Graphical Debug in Physical Design
Author(s): Pete Churchill [EdgeRate Consulting] |
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| TD2 - Efficient Verification Methodologies |
Creating HyperTransport Verification IP Using Vera
Author(s): Vijayalakshmi Pethachi, Jyotsna Menon, GuruPrasad Karaje [GDA Technologies], Ramnath S. [Xambala] |
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Formal Verification of a Packet Reordering Scheme Based on the HyperTransport Protocol
Author(s): John A. Thomson [Worcester Polytechnic Institute] |
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| TD3 - Transistor Level Design |
Library Modeling for Effective Leakage Management
Author(s): Rob Aitken, Scott Bordelon, Duane Champoux, Jim Shiffer [Artisan Components] |
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Optimizing Memory Power/Performance Tradeoffs
Author(s): Rob Aitken, Ravi Bhatia [Artisan Components] |
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| TD4 - Power Management and Low Power Design |
Area and Power Recovery without Sacrificing Timing
Author(s): Zia Khan, Imtiaz Hussain, Jackson Lee, Nai-Ying Chan [Intel Corp.] |
|
Optimization Of Leakage Power With PrimeTime (2nd Place - Best Paper)
Author(s): Krzysztof Kozminski [National Semiconductor Corp.] |
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| WA1 - Signal Integrity |
A Practical Approach to the Full-chip Dynamic IR Drop Verification with Synopsys Tools
Author(s): Wei Si Jiang, Myung Kong [National Semiconductor Corp.] |
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Addressing CrossTalk - Achieving Timing Closure
Author(s): Colin MacDonald, Anis Jarrar [Motorola Inc.] |
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PrimeTime SI Noise analysis
Author(s): Elisabeth Moseley [Synopsys Inc.], Ken Wong [Conexant Systems] |
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| WA2 - IP |
Power Management Techniques for Soft IP
Author(s): Peter Greenhalgh [ARM] |
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Technology Abstraction Eases Silicon Intellectual Property Portability
Author(s): Jason Pecor, Matt Weber [Silicon Logic Engineering] |
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| WA3 - Systemizing the EDA System |
ASIC/SOC Implementation Stations - Constructing Design Flows
Author(s): Daniel Tang [Exar Corporation] |
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Multi-Mode Constraint Management Methodology
Author(s): Baris Aksoy [Calix] |
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The Human ECO Compiler (1st Place - Best Paper)
Author(s): Steve Golson [Trilobyte Systems] |