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| User Papers and Presentations |
| MC1 - Physical Implementation Flows in DSM Technology |
Fixing Hold Violations in DSM Era
Author(s): Anand Rajagopalan [Texas Instruments, Inc.] |
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Logic and Physical Synthesis Methodology for High Performance VLIW/SIMD DSP Core
Author(s): Jagesh Sanghavi, Helene Deng, Tony Lu [Tensilica, Inc.] |
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RTL to Layout Implementation of OMAP Platform
Author(s): James SW Song, Minh Chau, Pallas Yang [Texas Instruments, Inc.], Kaijian Shi, Stewart Shankel [Synopsys, Inc.] |
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| MC2 - Static Timing Analysis - Signal Integrity: Methodology |
Noise Analysis Flow and Methodology with PrimeTime SI
Author(s): Chih-Tung Chen, Wilson Chan, Ying Gao, Xin Bao [QUALCOMM, Inc. ], Geoff Suzuki [Synopsys, Inc.] |
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Using SPDM Modeling and PrimeTime-SI to Perform Multi-voltage Timing Analysis
Author(s): David Tamura [National Semiconductor Corp.] |
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| MC3 - Libraries: You Can't Live with Them, You Can't Live without Them |
Library Considerations When Using PrimeTime SI for Static Crosstalk Analysis
Author(s): Jason McCampbell [Silicon Metrics Corp.] |
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So You Want to Make an ASIC: How to Pick a Foundry and ASIC Library
Author(s): Tim L Wilson [Intel Corp.] |
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| MD1 - Methods for Improving Product Development |
ACSkit - A Framework Based on ACS to Automate Synthesis Steps
Author(s): Marco Carlini, Fabio Breviario [ST Microelectronics] |
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Design Guidelines for Optimal Results in FPGAs and ASIC Prototypes
Author(s): Jennifer Stephenson [Altera Corp.] |
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Distributing System Studio Simulations on Compute Farms with LSF
Author(s): Arend Dittmer [Platform Computing Corp.], Thomas Komarek [Synopsys, Inc.] |
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| MD2 - Static Timing Analysis - Signal Integrity: Correlation |
Clock Skew Versus Data Skew Analysis in Launch to Capture Flip-Flop Pair Timing Paths to Verify Process Range Uniformity
Author(s): Jack Knutson [Independent] |
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Post Layout Static Timing Analysis of Xilinx Platform for Programmable Systems FPGA using PrimeTime
Author(s): Hamid Agah [Xilinx, Inc.] |
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| MD3 - VCS and Simulation Methodology |
A Simulation-based Approach to Skew and Jitter Testing - Addressing Interface Timing Issues During Functional Verification
Author(s): Alex Genusov, Steve Callahan [Zaiq Technologies] |
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Blazing Saddles: Getting the Performance Out of VCS (1st Place - Best Paper)
Author(s): Gregg Lahti, Gopal Varshney [Corrent Corp.], Tim Schneider [Synopsys, Inc.] |
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Save and Restore in VCS + Vera: How, Why and Where to use it
Author(s): VJ Sananda [DVXpress] |
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| MD4 - Physical Verification |
Structured Way of Developing Hercules Decks to Encourage Reusability
Author(s): Donald Smeltzer, Sheree Bautista, Sundari Kumar [Motorola Inc.] |
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Using Hercules DRC to Improve Reliability
Author(s): Donald Smeltzer, Sundari Kumar [Motorola Inc.] |
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| TA1 - Vera Testbench Design and Verification Methodology |
Block-Based ASIC Verification Using Vera
Author(s): Kevin Thompson [Cypress Semiconductor], Ladd Williamson [MicroWorks Inc.] |
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OpenVera Assertions for Functional Verification
Author(s): Jim Kornell [Cold Spring Engineering] |
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| TA2 - Static Timing Analysis - Signal Integrity: Implementation |
Challenges in the Hierarchical STA of a Low-Power 3G Wireless Application Platform
Author(s): James SW. Song, Satyendra R.P.Raju Datla, Yuanqiao Zheng [Texas Instruments, Inc.], Stewart Shankel, Kaijian Shi [Synopsys, Inc.] |
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Identifying, Prototyping and Fixing Crosstalk Induced Timing Violations with PT-SI and PC
Author(s): Kwamina Ewusie, Richard Nouri [Synopsys Inc.] |
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My Favorite DC/PT TCL Tricks
Author(s): Paul Zimmer [Cisco Systems] |
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| TA3 - Alternatives for Design and Verification: SystemC, System Verilog, PLI |
Chip Modeling Using C Languages & Verilog PLI - General Architecture
Author(s): Mohan Kumaraswamy, Manohar Natarajan [HCL Technologies Ltd.] |
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HDVL += (HDL & HVL) SystemVerilog 3.1 The Hardware Description AND Verification Language
Author(s): Stuart Sutherland [Sutherland HDL, Inc.], Don Mills [LCDM Engineering] |
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The Next Level of Abstraction: Evolution in the Life of an ASIC Design Engineer (Technical Committee Award)
Author(s): Rangarajan (Sri) Purisai, Sanjay Rekhi [Cypress Semiconductor] |
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| TA4 - Analog and Mixed Signal Methodologies |
A Multi-process Targetable Data Converter and its Automated Migration Flow
Author(s): Pallab Chatterjee [SiliconMap, LLC], Amit Gupta [Analog Design Automation, Inc.] |
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Functional Verification of Mixed Analog-Digital Design Using A Saber/Verilog Co-Simulation Environment
Author(s): Eric Zhang, Garry Shyu [LSI Logic] |
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Top-Down Design of a Mixed-Signal Power Converter IC
Author(s): Mark Muegge [iWatt Inc.] |
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| TB1 - Physical Design Methodologies |
Physical Compiler vs Astro: How Far Can We Push the Borderline?
Author(s): Davide Casalotto, Guido Repetto, Simone Ferri [STMicroelectronics] |
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ReShape's Astro-Based High Performance SoC Design Environment
Author(s): Paul Rodman [ReShape, Inc.] |
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| TB2 - Synthesis Optimized Source Code |
csrGen: Automated CSRs for ASIC/FPGA Processor Interfaces
Author(s): Chuck Benz [Chuck Benz ASIC and FPGA Design] |
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PERL SCRIPT - csrGen: Automated CSRs for ASIC/FPGA Processor Interfaces
Author(s): Chuck Benz [Chuck Benz ASIC and FPGA Design] |
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Predicting Routability at the RTL
Author(s): Jack Marshall [Tera Systems Inc. ] |
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Synthesis Optimized Universal Synchronous/Asynchronous Generic FIFO Design
Author(s): Edward Paluch [Sony Electronics, Inc.] |
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Synthesizable Finite State Machine Design Techniques Using the New SystemVerilog 3.0 Enhancements (2nd Place - Best Paper)
Author(s): Clifford Cummings [Sunburst Design, Inc.] |
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| TB3 - Design-for-Test |
Developing Test Sets by Exploiting DFT Compiler and TetraMAX ATPG
Author(s): DanusaDevi Vijayakumar, Michael Knieser [Indiana University Purdue University Indianapolis], Dan Weyer [Cisco Systems], Francis Wolff, Chris Papachristou [Case Western Reserve University] |
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Improving Runtime and Capacity of Scan Insertion and ATPG for Multimillion Gate Designs
Author(s): Amar Guettaf [Broadcom Corp.] |
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Scan and ATPG on a 20GB Duplex Network Processor
Author(s): Tim Ayres [Synopsys, Inc.], Prasad Mantri [Independent], Nagina Shetty [Silicon Access Networks, Inc.] |
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SCAN Patterns Size Reduction Using TetraMAX
Author(s): Mickey Oliel [National Semiconductor Corp.] |