SNUG San Jose 2003 Proceedings

2011|2010
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User Papers and Presentations
MC1 - Physical Implementation Flows in DSM Technology
Fixing Hold Violations in DSM Era
Author(s): Anand Rajagopalan [Texas Instruments, Inc.]
PaperPresentation

Logic and Physical Synthesis Methodology for High Performance VLIW/SIMD DSP Core
Author(s): Jagesh Sanghavi, Helene Deng, Tony Lu [Tensilica, Inc.]
PaperPresentation

RTL to Layout Implementation of OMAP Platform
Author(s): James SW Song, Minh Chau, Pallas Yang [Texas Instruments, Inc.], Kaijian Shi, Stewart Shankel [Synopsys, Inc.]
PaperPresentation

MC2 - Static Timing Analysis - Signal Integrity: Methodology
Noise Analysis Flow and Methodology with PrimeTime SI
Author(s): Chih-Tung Chen, Wilson Chan, Ying Gao, Xin Bao [QUALCOMM, Inc. ], Geoff Suzuki [Synopsys, Inc.]
PaperPresentation

Using SPDM Modeling and PrimeTime-SI to Perform Multi-voltage Timing Analysis
Author(s): David Tamura [National Semiconductor Corp.]
PaperPresentation

MC3 - Libraries: You Can't Live with Them, You Can't Live without Them
Library Considerations When Using PrimeTime SI for Static Crosstalk Analysis
Author(s): Jason McCampbell [Silicon Metrics Corp.]
PaperPresentation

So You Want to Make an ASIC: How to Pick a Foundry and ASIC Library
Author(s): Tim L Wilson [Intel Corp.]
PaperPresentation

MD1 - Methods for Improving Product Development
ACSkit - A Framework Based on ACS to Automate Synthesis Steps
Author(s): Marco Carlini, Fabio Breviario [ST Microelectronics]
PaperPresentation

Design Guidelines for Optimal Results in FPGAs and ASIC Prototypes
Author(s): Jennifer Stephenson [Altera Corp.]
PaperPresentation

Distributing System Studio Simulations on Compute Farms with LSF
Author(s): Arend Dittmer [Platform Computing Corp.], Thomas Komarek [Synopsys, Inc.]
PaperPresentation

MD2 - Static Timing Analysis - Signal Integrity: Correlation
Clock Skew Versus Data Skew Analysis in Launch to Capture Flip-Flop Pair Timing Paths to Verify Process Range Uniformity
Author(s): Jack Knutson [Independent]
PaperPresentation

Post Layout Static Timing Analysis of Xilinx Platform for Programmable Systems FPGA using PrimeTime
Author(s): Hamid Agah [Xilinx, Inc.]
PaperPresentation

MD3 - VCS and Simulation Methodology
A Simulation-based Approach to Skew and Jitter Testing - Addressing Interface Timing Issues During Functional Verification
Author(s): Alex Genusov, Steve Callahan [Zaiq Technologies]
PaperPresentation

Blazing Saddles: Getting the Performance Out of VCS (1st Place - Best Paper)
Author(s): Gregg Lahti, Gopal Varshney [Corrent Corp.], Tim Schneider [Synopsys, Inc.]
PaperPresentation

Save and Restore in VCS + Vera: How, Why and Where to use it
Author(s): VJ Sananda [DVXpress]
PaperPresentation

MD4 - Physical Verification
Structured Way of Developing Hercules Decks to Encourage Reusability
Author(s): Donald Smeltzer, Sheree Bautista, Sundari Kumar [Motorola Inc.]
PaperPresentation

Using Hercules DRC to Improve Reliability
Author(s): Donald Smeltzer, Sundari Kumar [Motorola Inc.]
PaperPresentation

TA1 - Vera Testbench Design and Verification Methodology
Block-Based ASIC Verification Using Vera
Author(s): Kevin Thompson [Cypress Semiconductor], Ladd Williamson [MicroWorks Inc.]
PaperPresentation

OpenVera Assertions for Functional Verification
Author(s): Jim Kornell [Cold Spring Engineering]
PaperPresentation

TA2 - Static Timing Analysis - Signal Integrity: Implementation
Challenges in the Hierarchical STA of a Low-Power 3G Wireless Application Platform
Author(s): James SW. Song, Satyendra R.P.Raju Datla, Yuanqiao Zheng [Texas Instruments, Inc.], Stewart Shankel, Kaijian Shi [Synopsys, Inc.]
PaperPresentation

Identifying, Prototyping and Fixing Crosstalk Induced Timing Violations with PT-SI and PC
Author(s): Kwamina Ewusie, Richard Nouri [Synopsys Inc.]
PaperPresentation

My Favorite DC/PT TCL Tricks
Author(s): Paul Zimmer [Cisco Systems]
PaperPresentation

TA3 - Alternatives for Design and Verification: SystemC, System Verilog, PLI
Chip Modeling Using C Languages & Verilog PLI - General Architecture
Author(s): Mohan Kumaraswamy, Manohar Natarajan [HCL Technologies Ltd.]
PaperPresentation

HDVL += (HDL & HVL) SystemVerilog 3.1 The Hardware Description AND Verification Language
Author(s): Stuart Sutherland [Sutherland HDL, Inc.], Don Mills [LCDM Engineering]
PaperPresentation

The Next Level of Abstraction: Evolution in the Life of an ASIC Design Engineer (Technical Committee Award)
Author(s): Rangarajan (Sri) Purisai, Sanjay Rekhi [Cypress Semiconductor]
PaperPresentation

TA4 - Analog and Mixed Signal Methodologies
A Multi-process Targetable Data Converter and its Automated Migration Flow
Author(s): Pallab Chatterjee [SiliconMap, LLC], Amit Gupta [Analog Design Automation, Inc.]
PaperPresentation

Functional Verification of Mixed Analog-Digital Design Using A Saber/Verilog Co-Simulation Environment
Author(s): Eric Zhang, Garry Shyu [LSI Logic]
PaperPresentation

Top-Down Design of a Mixed-Signal Power Converter IC
Author(s): Mark Muegge [iWatt Inc.]
PaperPresentation

TB1 - Physical Design Methodologies
Physical Compiler vs Astro: How Far Can We Push the Borderline?
Author(s): Davide Casalotto, Guido Repetto, Simone Ferri [STMicroelectronics]
PaperPresentation

ReShape's Astro-Based High Performance SoC Design Environment
Author(s): Paul Rodman [ReShape, Inc.]
PaperPresentation

TB2 - Synthesis Optimized Source Code
csrGen: Automated CSRs for ASIC/FPGA Processor Interfaces
Author(s): Chuck Benz [Chuck Benz ASIC and FPGA Design]
PaperPresentation

PERL SCRIPT - csrGen: Automated CSRs for ASIC/FPGA Processor Interfaces
Author(s): Chuck Benz [Chuck Benz ASIC and FPGA Design]

Predicting Routability at the RTL
Author(s): Jack Marshall [Tera Systems Inc. ]
PaperPresentation

Synthesis Optimized Universal Synchronous/Asynchronous Generic FIFO Design
Author(s): Edward Paluch [Sony Electronics, Inc.]
PaperPresentation

Synthesizable Finite State Machine Design Techniques Using the New SystemVerilog 3.0 Enhancements (2nd Place - Best Paper)
Author(s): Clifford Cummings [Sunburst Design, Inc.]
PaperPresentation

TB3 - Design-for-Test
Developing Test Sets by Exploiting DFT Compiler and TetraMAX ATPG
Author(s): DanusaDevi Vijayakumar, Michael Knieser [Indiana University Purdue University Indianapolis], Dan Weyer [Cisco Systems], Francis Wolff, Chris Papachristou [Case Western Reserve University]
PaperPresentation

Improving Runtime and Capacity of Scan Insertion and ATPG for Multimillion Gate Designs
Author(s): Amar Guettaf [Broadcom Corp.]
PaperPresentation

Scan and ATPG on a 20GB Duplex Network Processor
Author(s): Tim Ayres [Synopsys, Inc.], Prasad Mantri [Independent], Nagina Shetty [Silicon Access Networks, Inc.]
PaperPresentation

SCAN Patterns Size Reduction Using TetraMAX
Author(s): Mickey Oliel [National Semiconductor Corp.]
PaperPresentation

Tutorials
MA1
Synthesis Highlights in Design Compiler 2003
Author(s):
Tutorial

MA2/MB2
Synopsys DFT Compiler SoCBIST Introduction, TetraMAX & DFT Compiler Updates
Author(s):
Tutorial

MA3
OpenVera Coding Style Guidelines
Author(s):
Tutorial

MB1
Leakage Power Optimization Using Power Compiler and Multi-Threshold CMOS Technologies
Author(s):
Tutorial

MB3
Solving Equivalence Checking Challenges by Improving Tool Interoperability
Author(s):
Tutorial

WA1
Physical Compiler Highlights in 2003.03
Author(s):
Tutorial

WA2
PrimeTime and PrimeTime SI Technology Update
Author(s):
Tutorial

WA3
Designing Multi-processor Platforms at the Transaction-Level with System Studio
Author(s):
Tutorial

WA4
Apollo-to-Astro Migration
Author(s):
Tutorial

WB1
Advanced Avoidance and Analysis of Signal-Integrity Issues
Author(s):
Tutorial

WB2/WC2
Smart Verification Methodology
Author(s):
Tutorial

WB3
Parasitic Extraction at 90nm with Star-RCXT
Author(s):
Tutorial

WC1
Astro Clock Tree Synthesis
Author(s):
Tutorial

Speech
Guest Speaker
The Design Challenges
Author(s): Mike Muller [ARM]
Paper

Keynote Address
Electronic Design Under Max Pressure
Author(s): Aart de Geus, Chairman and CEO [Synopsys, Inc.]
Paper