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| User Papers and Presentations |
| A5: NanoTime: The Next Generation Transistor-Level Analysis Solution for Custom Design |
Bone: Custom Design Sizing Optimization Flow using NanoTime (1st Place - Best Paper)
Author(s): Gideon Reisfeld, Gregory Zabolotov [Intel] |
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| B1 - Verification Methodology |
Analyze your OpenVera Code. Facilitate Code Reuse through Coding Guidelines and Code Documentation
Author(s): Yossi Ginzburg, Eyal Skulsky [Qualcomm] |
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Chip Level Methodology for Fully Reuse Block Level Environments
Author(s): Shlomi Sperber [TI] |
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Generic RVM Infrastructure
Author(s): Amit Pessach, Rachel Menes [Cisco] |
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| B3 - Physical Design |
A PrimeTime Based Net-Switching flow
Author(s): Alexander Sudakov, Efrat Rachevsky [Marvell] |
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MTC – Synthesis with Minimal Timing Constraints for Early Design
Author(s): Yossi Avrahami, Eyal Laufer [Intel] |
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Resolving Critical Formal Verification Issues via Synopsys SVF
Author(s): Amit Barzilay [Mplicity] |
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The Advantages of Using PrimeTime Distributed Multi Scenario Analysis (DMSA)
Author(s): Moshe Ashkenazi, Rafy Diaz [Texas Instruments] |
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| B5 -Analog Mixed-Signal |
HSIM-VCS-SystemVerilog Verification Flow for Image Sensor Innovative Chip Design
Author(s): Vladimir Polyak [Advasense], Isaac Zafrany [Synopsys] |
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Report Manager - Visualizing of HSIM Circuit Checks Results
Author(s): Ronen Moldovan [Saifun] |
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| C1 - Functional Verification Techniques |
Are you Satisfied with your Constraints? Eight Ways to Misuse Vera Solver
Author(s): Yossi Ginzburg, Eyal Skulsky, Ziv Baum, Tzahi Sabo [Qualcomm] |
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From Tools to Flow: Low Power Architecture Verification Using System Verilog
Author(s): Arik Rachevsky [Marvell] |
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How to Code Functional Coverage in SystemVerilog
Author(s): Akiva Michelson [ACE Verification] |
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| C3 - Taming the ECO Beast: Synopsys’ ECO Solution Overview |
Beyond the Human ECO Compiler
Author(s): Itai Yarom [Intel] |
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Low Impact ECO Methodology
Author(s): Dan Saad [Texas Instruments] |
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| C4 - Gate-Level Power Analysis using PrimeTime-PX |
Primetime-PX Integration in Zoran Power Flow
Author(s): Elon Rot [Zoran] |
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| C5 - Process Variation and Standard Cell Libraries |
Characterization: The Key to Accurate Simulation
Author(s): Alex Weinberg , Boris Mishori [Tower Semiconductor] |