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Speeches

Keynote Speech

SNUG Israel 2004 Keynote: Tough Techonomics!
Author(s): Dr Aart de Geus - Chairman of the Board & CEO [Synopsys Inc]

Paper

User Papers and Presentations

A1 - Functional Verification Techniques

ABV (Assertion Based Verification) - From concept to Reality via OVA
Author(s): Ilan Lisha, Doron Stein [CSI - Cisco Systems Israel]

Paper

Presentation

Complex SoC Validation using Synopsys DesignWare Verification IP and Vera
Author(s): Tomer Labin [Discretix]

Presentation

Using VERA Random Constrain Engine to Test Complex MPEG4 Chips (1st Place - Best Paper)
Author(s): Doron Meiraz [Emblaze Semiconductor], Gal Algavish [Independent]

Paper

Presentation

A2 - Analog Verification Techniques

Full Custom SRAM Design for Multimedia Application in 0.18u
Author(s): Oren Katzir, Kobi Steiner, Gadi Lehana [Silicon Design Systems LTD]

Presentation

B1- Physical Design 1

Dune Networks Implementation of Filp Chip Design in 130 nm Technology
Author(s): Zachi Feldman [Dune Networks]

Paper

Presentation

Multi Power VDD Flow for Complex Designs
Author(s): Leonid Tsukerman, Rafi Zagury [Intel - PTK]

Paper

Presentation

The Challenge of a Complex Chip Level Routing using the Columbia/AstroIU
Author(s): Eli Kraus [Analog Devices Israel DSP]

Paper

Presentation

B2 - Physical Design 2

Automatic DFM Flow for Unit Level using Hercules & Apollo
Author(s): Albert Yankelovich [Mellanox]

Paper

Presentation

From RTL to GDS using Synopsys Flow Within Less Than 10 Weeks
Author(s): Yaron Lavi [Intel ICGH]

Paper

Presentation

C1 - Physical Synthesis

ECO Flow - Using Physical Compiler
Author(s): Niv Margalit [CSI - Cisco System Israel]

Paper

Presentation

Minimum Physical Constraints in Physical Synthesis Flow
Author(s): Roy Bar [ParthusCeva Inc]

Presentation

Secrets of High-Speed Design or How to Reach 1.0 GHz Cycle Time with 0.13 um Technology
Author(s): Oleg Milter [Intel Corporation]

Paper

Presentation

C2 - Design for Test

A Hold-Buffer Reduction Algorithm for Scan-Chain Timing Closure
Author(s): Alex Bronfer, Rafy Diaz, Max Nigri [Texas Instruments Short Distance Wireless Israel]

Paper

Presentation

Failure Analysis by TetraMAX-Diagnosis
Author(s): Benny Rosen [Independent]

Presentation

Paper Only

Custom Aligners Clock Tree Methodology Using Physical Compiler
Author(s): Dan Saad, Yossi Asher [Motorola Semiconductors Israel, VLSI DSP]

Paper

Tutorials

Galaxy Implementation Platform - DC, Jupiter, PC and Astro Update
Author(s):

Tutorial

Static Timing Analysis, Signal Integrity and Equivalence Checking Updates
Author(s):

Tutorial