SNUG India 2014 Proceedings

Speeches
Keynote Address
Designing Change into Semiconductor Techonomics
Author(s): Dr. Aart de Geus, Chairman and co-CEO, Synopsys

System Design Challenges in the Connected World
Author(s): S. Balajee, Vice President, DS India Labs, Samsung Research Institute Bangalore
Keynote

User Papers and Presentations
TA1: IC Design: Implementation - Synopsys User and Tutorial Sessions
TA1.2 User: 28nm vs 20nm: A CAD Methodology Perspective
Author(s): Suresh Raman - Xilinx, Babitha Kunta - Synopsys
PaperPresentation

TA2: IC Design: Implementation - Synopsys User Session
TA2.1 User: Innovative Techniques to Achieve Optimal QoR with Faster Design Closure Cycle on a Multimillion SoC (Best Paper Award)
Author(s): Sitharam Ayathu, Pranjal Tiwari, Sailesh Vanama - LSI R&D India Pvt. Ltd., Gaurav Ganeriwal - Synopsys
PaperPresentation

TA2.2 User: Advanced ECO Methodology for ARM Core Subsystem
Author(s): Nitin Kaushik - STMicroelectronics, Vikas Garg - Synopsys
PaperPresentation

TA2.3 User: Meeting Clock Requirements for High Frequency Design
Author(s): Jake Tomy, Manu Mammen Varghese - Broadcom, Gaurav Ganeriwal, Rajesh Patchala - Synopsys
PaperPresentation

TA3: Synopsys User & Tutorial Sessions
TA3.1 User: A Practical Approach to Achieve Tighter Correlation and QoR From Synthesis Through P&R for a 28nm Design
Author(s): Tapan Bhandari, Vishal Jayantilal Katba, Aravind Ramanujam - Qualcomm, Umesh Ravjibhai Gajera - Synopsys
PaperPresentation

TB1: IC Verification - Synopsys User Sessions
TB1.1 User: Interrogating Formal Environment: Uncovering Hidden Details and Weaknesses
Author(s): Venkata Ramanamurthy Barala, Arun Prakash C.S, Jebin Vijai - Qualcomm Ankit Garg - Synopsys
PaperPresentation

TB1.2 User: Unified Verification Flow for Complex Low-Power Designs
Author(s): Abhijeet Chandratre, Caesar Deka, Anand Shanmugam Sundararajan, Ramachandiran V - NVIDIA
PaperPresentation

TB1.3 User: A Novel Approach to Significant Reduction in Time to First Test Using Configurable SoC Testbenches and VIP Reuse
Author(s):
PaperPresentation

TB1.4 User: Accelerated Verification of a MIPI CSI2 System Using CSI2 Verification IP
Author(s): Akhileshwar Dhiman, Gaurav Gupta, Shreya Singh - Freescale Semiconductor, Dipesh Handa - Synopsys
PaperPresentation

TC2: Systems and IP - Synopsys Tutorial & User Session
TC2.2 User: Mechatronics System Modeling: Saber
Author(s): Manish Bansal, Saurabh Srivastava, Rahul Kumar, Akhilesh Chandra Mishra - STMicroelectronics
PaperPresentation

TC2.3 User: On the Fly Donut Formation in Compiled HD Memory to Enable Analysis of Biggest Instance
Author(s): Darvinder Singh, Isha Garg, Vineet Sachan - AMD
PaperPresentation

TD1: IC Design: Low Power - Synopsys User and Tutorial Sessions
TD1.1 User: Modeling and Implementation of Low-Power Intent for Complex SoC Using UPF2.0
Author(s): Shashank Bhonge, Vaishali Huilgol, Vinod Reddy - Xilinx
PaperPresentation

TD1.2 User: Library-Level Low-Power Verification Techniques for ARM Artisan Physical IP
Author(s): Venkatesh Bharati Krishnamurthy, Divyeshkumar Vora - ARM
PaperPresentation

TD2: IC Design: Low Power - Synopsys User & Tutorial Session
TD2.1 User: Case Study of Using Verdi Signoff LP for Low Power Checks
Author(s): Hitesh Nijhawan - STMicroelectronics, Vikas Garg - Synopsys
PaperPresentation

TD2.2 User: A Recipe to Implement and Verify Low-Power Architecture
Author(s): Alpana Bastimane, Varaprasad Mailapalli - LSI R&D India Pvt. Ltd.
PaperPresentation

TD2.3 User: Efficient Static and Formal Verification Closure of Low-Power Designs (Best Paper Award)
Author(s): Satyanarayana A, Rakesh Madala, Shilpi Varshney - AMD
PaperPresentation

WA1: IC Verification - Synopsys User Sessions
A Novel Approach to Estimate Simulation Acceleration Performance Gain in an Emulator
Author(s):
PaperPresentation

WA1.2 User: Transactor-Based Verification of Baseband SoCs
Author(s): Santosh Kalakonda, Jayaprakash Madhiraju, Raju Manjunath, Sriram Rajagopalan - Broadcom
PaperPresentation

WA1.3 User: An Alternate Approach to Address Emulation of Complex Clocking Systems in FPGA Platforms (Best Paper Award)
Author(s): Venkatesh Natarajan - Texas Instruments; Ashwani Sharma - Synopsys
PaperPresentation

WB1: IC Design: Signoff - Synopsys User and Tutorial Sessions
WB1.2 User: PrimeTime Based Efficient Approach for CDC and MTBF Checks in a Complex SoC (Best Paper Award)
Author(s): Saksham Pant - NVIDIA
PaperPresentation

WB1.3 User: Next Generation STA Techniques for 140+ Million Gates Multi-Voltage Design
Author(s): Sachin Gupta, Parth Lakhiya - LSI R&D India Pvt. Ltd., Ramanuj Mishra - Synopsys
PaperPresentation

WB2: IC Design: Signoff - Synopsys User Session
WB2.1 User: SMVA-Based Efficient Approach for Timing Closure of a Complex Multi-Voltage DVFS Design
Author(s): Amitesh Khongal, Anshuman Seth, Shilpa Thakur - NVIDIA
PaperPresentation

WB2.2 User: Faster Timing Closure in Complex SoCs Using Mode Merging
Author(s): Deepshikha Moudgil, Mohit Verma - STMicroelectronics; Vikas Choudhary - Synopsys
PaperPresentation

WB3: IC Design: Signoff - Synopsys User and Tutorial Session
WB3.2 User: Ensuring Robust Rail Analysis
Author(s): Venkatesh Bharati Krishnamurthy, Kevin Vaz - ARM
PaperPresentation

WB3.3 User: Design Closure with PrimeTime Physical-Aware ECO Fixing and MPI
Author(s): Amar Pallam, Roopesh Paruchuri, Raghu Pattipati, Rajit Seahra - AMD
PaperPresentation

WC1: Custom Design and AMS Verification - Synopsys User and Tutorial Sessions
WC1.2 User: A Novel Approach Towards Power Characterization of Compiled Memory IPs
Author(s):
PaperPresentation

WC1.3 User: Runtime Reduction in High Q Circuits Using Harmonic Balance (HB) Algorithm in HSPICE
Author(s): Shiv Harit Mathur, Anand Sharma - SanDisk, Suresh Vaiyapuri - Synopsys
PaperPresentation

WC2: Custom Design and AMS Verification - Synopsys User Session
WC2.1 User: Solving Challenges in Timing Model Development for Custom Memories Using FineSim
Author(s): Shrinidhi Bhat, Ravi Kumar D S, Prabhu Mohan - Microsemi
PaperPresentation

WC2.2 User: DDR4 Functional Verification With XA-VCS
Author(s): Mukta Goyal, Madhukar Nakka, Siva Charan Nimmagadda - Xilinx, Rohini Nandi - Synopsys
PaperPresentation

WC2.3 User: Block Level Electromigration for More Effective Reliability Check In Full Custom IPs (Best Paper Award)
Author(s): Atul Bhargava, Radhika Gupta, Monika Rawat - STMicroelectronics, Mridul Sengupta - Synopsys
PaperPresentation

WC3: Custom Design and AMS Verification - Synopsys User and Tutorial Session
WC3.1 User: A Correct by Construction Layout Placement Flow for Hierarchical Mixed Signal Designs
Author(s):
PaperPresentation

WD1: IC Design: Test -Synopsys User and Tutorial Sessions
WD1.2 User: Serializer Mechanism in Asymmetric Scan Configuration (Best Paper Award)
Author(s): Mudasir Kawoosa, Rajesh Mittal - Texas Instruments
PaperPresentation

WD1.3 User: BIST Area Optimization Using SMS 4.x
Author(s): Abhinand K, Bhavi Panchal, Nachiket Soman - Open Silicon
PaperPresentation

WD1.4 User: Power Reduction Methods in Multicore SoC Scan Architecture
Author(s): Thirukumaran Natrayan, Shyam Sundar, Satishchandra Rao - Analog Devices Inc
PaperPresentation

WD2: User Paper
WD2.2 User: Debugging Complex Run Time Issues Using ProtoLink
Author(s): Rajesh Udenia, Vipin Verma - Freescale Semiconductor
PaperPresentation

WD3: FPGA - User and Tutorial Session
WD3.2 User: Composed SoC Validation
Author(s): Shreepad Hardas - Open-Silicon
PaperPresentation

WD3.3 User: IP Design - Efficient and Fast Prototyping and Porting to ASIC Using Synopsys Tools (Best Paper Award)
Author(s): Prasanth R I, Thomas Varghese - Mindtree Ltd.
PaperPresentation

Publication Only
Publish Only
Achieving Extreme Compression for Next Gen SoC Designs
Author(s): Rajendra Kumar Reddy - NVIDIA
Paper

Automated Custom Placement and Routing for Advanced Nodes
Author(s):

Beyond CODEC Scan DFT Architecture for Pin-Limited Large SoCs
Author(s): Tushar Khadtare, Dr. Pradip Thaker - GEO Semiconductor
Paper

Bottom Up Hierarchial Floorplanning V/S Top Down Floorplanning
Author(s): Vikram Mouneshwar - LSI India Reasearch & Development Pvt Ltd.
Paper

Customized Characterization of Complex Circuits Using SiliconSmart ACE
Author(s): Anand Sharma, Ramakrishnan Subramanian - SanDisk
Paper

Implementation of VA Feedthrough
Author(s): Tejkumar Korat, Bhushan Kapadnis - LSI India Reasearch & Development Pvt Ltd.
Paper

New Methodology for ESP-CV Functional Equivalence Checking for FinFET Based Memories
Author(s): Himanshu Garg, Pratik Satasia, Abhishek CR - ARM; Dave Hedges - Synopsys
Paper

Performance Matters: Why DDR3 Standalone Verification is Not Sufficient
Author(s): Navajeevan Biswaprakash, Yogesh Mittal - Freescale Semiconductor
Paper

Quick, Re-Usable and Cost Effective Approach to Create Accurate Models Using Synopsys Platform Architect Framework for Early System Level Performance Analysis
Author(s): Saurin Patel, Baljinder Sood - Freescale Semiconductor
Paper

TA Analyzer Cockpit
Author(s): Hitesh Nijhawan - STMicroelectronics
Paper

Unified Environment and Infrastructure for Simulation, Emulation and Silicon Validation
Author(s): Gopesh Goyal, Rajesh LG, Siva Kumar R, Rajesh GSVR - Cisco
Paper

VCS Optimization Techniques for Multi-Chip Simulations
Author(s): Debashis Biswas - Cisco
Paper

Tutorials
TA1: IC Design: Implementation - Synopsys User and Tutorial Sessions
TA1.1 Tutorial: IC Compiler II and the Power of 10x: A Product Walk-Through
Author(s): Sanjay Bali, Neeraj Kaul - Synopsys

TA1.3 Tutorial: Advanced Custom Routing Using Galaxy Custom Router
Author(s): Rajagopal Sundararaman - Synopsys, Girish Prabhu – NVIDIA
PaperTutorial

TA3: Synopsys User & Tutorial Sessions
TA3.2 Tutorial: Emerging Node Design with IC Compiler
Author(s): Gaurav Ganeriwal - Synopsys
Tutorial

TB2: IC Verification - Synopsys Tutorial Session
TB2.1 Tutorial: Taking Debug Productivity to the Next Level with Your Own Verdi Apps
Author(s): Rich Chang - Synopsys
Tutorial Video

TB3: IC Verification - Synopsys Tutorial Session
TB3.1 Tutorial: Verification Closure Flow
Author(s): Amit Sharma - Synopsys
Tutorial

TB3.2 Tutorial: Advanced Verification Techniques Applied to ARM AMBA 4 / AMBA 5 Protocol-Based SoCs
Author(s): Satyapriya Acharya - Synopsys
Tutorial

TC1: Systems and IP - Synopsys Tutorial Sessions
TC1.1 Tutorial: Physical IP Development on FinFET - There's Nothing Planar About It!
Author(s): Amit Khanuja - Synopsys
Tutorial

TC1.2 Tutorial: Performance Analysis for the Synopsys DesignWare Universal DDR Memory Controller Using Synopsys Platform Architect MCO
Author(s): Asheesh Khare - Synopsys
Tutorial

TC2: Systems and IP - Synopsys Tutorial & User Session
TC2.1 Tutorial: Integrating USB 3.1 in Your Next SoC Design
Author(s): Didier Leclercq - Synopsys
Tutorial

TC3: Systems & IP - Synopsys User and Tutorial Sessions
TC3.1 Tutorial: Ultra-Low Power Processors and Subsystems for IoT
Author(s): Hemal Mehta - Synopsys
Tutorial

TC3.2 Tutorial: Best-In-Class Foundation IP for Different Types of Processor Cores
Author(s): Amit Khanuja - Synopsys
Tutorial

TD1: IC Design: Low Power - Synopsys User and Tutorial Sessions
TD1.3 Tutorial: Low-Power Design Implementation
Author(s): Renu Mehra - Synopsys
Tutorial

WA2: IC Verification - Synopsys User and Tutorial Sessions
WA2.1 Vision: Next Order of Productivity and Performance Through Technology and Integration with Verification Compiler
Author(s): Dr. Arturo Salz - Synopsys Scientist

WA3: IC Verification - Synopsys Tutorial Session
WA3.1 Tutorial: Increase Low-Power Verification Productivity
Author(s): Amol Herlekar - Synopsys
Tutorial

WB1: IC Design: Signoff - Synopsys User and Tutorial Sessions
WB1.1 Tutorial: PrimeTime Best Practices and Feature Updates
Author(s): Natarajan Sridharan - Synopsys
Tutorial

WB3: IC Design: Signoff - Synopsys User and Tutorial Session
WB3.1 Tutorial: PrimeTime Advanced Waveform Propagation
Author(s): Alireza Kasnavi - Synopsys
Tutorial

WC1: Custom Design and AMS Verification - Synopsys User and Tutorial Sessions
WC1.1 Vision: Mixed-Signal Design Solution - At the Confluence of Analog and Digital
Author(s): Ravi Tembhekar - Synopsys

WC3: Custom Design and AMS Verification - Synopsys User and Tutorial Session
WC3.2 Tutorial: Transistor Level Static and Dynamic Circuit Analysis, an ERC Solution for Deep Sub-Micron Low-Power Custom Digital, Memory and Analog IP Designs
Author(s): Vivek Sharma - Synopsys
Tutorial

WD1: IC Design: Test -Synopsys User and Tutorial Sessions
WD1.1 Tutorial: Low DPPM and Low Cost Testing for All Process Nodes and FinFETs
Author(s): Jyotirmoy Saikia - Synopsys
Tutorial

WD2: FPGA - Synopsys User & Tutorial Session
WD2.1 Tutorial: Putting IP and Subsystem Prototyping on the Fast Track
Author(s): Suresh Kumar, Didier Leclercq - Synopsys
Tutorial

WD3: FPGA - User and Tutorial Session
WD3.1 Tutorial: Better, Faster, Sooner: Tips and Tricks to Efficiently Achieve Timing Performance Goals
Author(s): Madhav Chikodikar - Synopsys
Tutorial

Combo
WB2: IC Design: Signoff - Synopsys User Session
WB2.3 Tutorial: Addressing ECO Bottlenecks in Parasitic Extraction Using Advanced Flows in StarRC
Author(s): Sandeep Parswanath - Qualcomm, Ananda Veerasangaiah - Synopsys
PresentationTutorial

User Presentation
WA1: IC Verification - Synopsys User Sessions
WA1.4 User: eXtinguishing the 'X' Fire from RTL Testbench and Design to Prevent Gate Level Testbench Bring-Up Heartburns
Author(s): Harsh Garg, Nitin Jaiswal - Freescale Semiconductor
PaperPresentation