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| User Papers and Presentations |
| FA1: Vision Session & User Papers |
User: Performance Oriented Re-Spin Implementation Within Tight Schedule
Author(s): Sridharan Ramachandran, Ramakrishnan Varadhan [Qualcomm] |
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User: Super IP - Cost Efficient Concurrent Physical Implementation of Multiple Designs
Author(s): Hari Krishnamoorthy, Durga Parimi, Gowryshankar Shanmugham, Venkat Swamy Bonam [Texas Instruments] |
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| FA2: Tutorial & User Papers |
Achieving Leakage Power Savings Through Final-Stage Leakage Recovery
Author(s): Pramod Sripathi, Suresh Raman, [Xilinx], Vivekanandan Muthuswami [Synopsys] |
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Improving the Productivity While Retaining Predictability and Controllability in High Performance Multi-Core Server CPU Physical Integration
Author(s): Naresh Vijay, Venkataraman Shankar, Mysore Sriram [Intel] |
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| FA3: User Papers |
User: 28nm Challenges for DFM, Timing and Xtalk Aware Routing
Author(s): Yousuff Shariff, Inderjeet Kaur, Yaseer Azeez Mohammed [AMD] , Sudheer Chelluri [Synopsys] |
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User: A Smart Step Density Flow for SoC Design (1st Place - Best Paper; IC Physical Design)
Author(s): Madan Lal, Veerakumar Pitchiah [Intel] |
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User: Conquering Challenges in Design Closure of Multi Power Domain Macro Dominated
Author(s): Nagabharana Teeka, Anup Rajput, Kishore Kumar Robbi, Sanjana Sundaresh [Texas Instruments] |
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| FB1: Tutorial & User Papers |
User: FPGA Debug Made Easy Using Synopsys' Identify Clock Gating Approach
Author(s): Suyash Ranjan, Abhijit V A, [NVIDIA] |
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User: High-Speed Prototyping Techniques for Multi FPGA Prototypes of Complex SoCs (1st Place - Best Paper; FPGA Design)
Author(s): Ameet Bagwe, Kanad Kanhere [Texas Instruments] |
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| FB2: Tutorial & User Papers |
User: Advanced At-Speed Emulation using Synopsys HAPS Platform
Author(s): Praveen Goyal, Upma Sharda, Gaurav Davra [Qualcomm], Darshan Patil [Synopsys] |
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User: Friendly Prototype design and Prototype Friendly Design
Author(s): Dario Catalano [STMicroelectronics], Pradeep Kumar M P [Synopsys] |
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| FC1: Tutorial & User Papers |
User: Active Net Extraction for Memory Characterization
Author(s): Sindhagatta Asha [Qualcomm], Raj Sundararaman [Synopsys] |
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User: Efficient Tuning of Sigma Delta Using XA
Author(s): Vigyan Jain [ST Microelectronics], Rakesh Shenoy Panemangalore [Synopsys] |
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| FC2: Tutorial & User Papers |
User: Efficient Power and Signal Reliability Analysis of Large Memories
Author(s): Biswa Sahoo, Vinod Rach, Sagar Suresh [LSI], Sateesh Chandramohan [Synopsys] |
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User: Fast 3D Extractors for Getting Atto-Farad Resolution on Large Designs at Advanced Technology Nodes
Author(s): Atul Bhargava, Chittoor Parthasarathy, Neeraj Kapoor, Siddharth Gupta [ST Microelectronics] |
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| FC3: User Papers |
User: Closing the Verification Loop for Complex CMOS032 Embedded Static RAM/ROM Designs
Author(s): Sunil Kumar, Prakhar Raj Gupta [ST Microelectronics], Rakesh Shenoy Panemangalore [Synopsys] |
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User: Enabling Efficient AMS Co-simulation of Mixed-signal SoC with Analog and Power Management Integration (1st Place - Best Paper; Custom Design and AMS Verification)
Author(s): Pooja Sundar, Lakshmanan Balasubramanian, Sandeep Tare [Texas Instruments], Charles Jiang [Synopsys] |
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User: Validation Efficiency Improvement Using Fast Spice Simulator for High Speed Serial IOs
Author(s): Kumaran Natarajan, Mugdha Alurkar, Pravas Pradhan [Intel], Sateesh Chandramohan [Synopsys] |
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| TA1: Tutorials & User Papers |
User: Automation Package for Register Constrained Randomization and Coverage Convergence
Author(s): Venu Gopal Paripelly, Robin Mathew, Kiran Kumar Mada, Atul Kotwal [CISCO] |
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User: Practical Considerations in Reusing OVM Based VIPs and a Quick UVM Apercu
Author(s): Kishor Kulkarni [Intel], Srinivasan Venkataramanan [CVC Pvt Ltd], Amit Sharma [Synopsys] |
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| TA2: User Papers |
User: Challenges and Approaches for Functional Coverage in SOC Verification Environments
Author(s): Manikandan Subramanian, Ron Jacob, Sasidhar Dudyala, Srishan Thirumalai [LSI] |
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User: Heuristic Ranking Techniques for Efficient Analysis of Code Coverage Data
Author(s): Ishwar Agarwal, Srilatha Chandrasekaran, Dixit Betaraya [Intel] |
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User: Jitter Modeling in RTL Simulation - A Way to Ensure 1st Pass Silicon (1st Place - Best Paper; IC Verification)
Author(s): Vidit Babbar, Arvind Kumar, Kalpesh Shah, Vikas Lakhanpal [Texas Instruments] |
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| TA3: User Papers |
User: Automated Regression Report Generation Flow Using Verification Planner
Author(s): Suresh Bandaru, Shivani Upasani, Imran Ali, Jayendra Dwaraka Bhamidipatti [LSI] |
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User: Challenges in FUSION Chip Verification - CPF to UPF Conversion and LP Methodology Adaptation
Author(s): Sabyasachi Pradhan [AMD], Kartik Jain [Synopsys] |
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| TB1: Vision Session & User Papers |
User: Full Chip Power Analysis Using PT-PX at Various Stages of SoC Design
Author(s): Krishnan Unni, Deepak Tottempudi, Saj Kapoor, Shrinivas M V [Analog Devices] |
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User: Interconnect SSTA Plus Plus
Author(s): Ajoy Mandal , Arvind N V [Texas Instruments] |
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| TB2: Tutorial & User Paper |
User: Evolving Faster and Better Closure Strategy for LP SoC IR Drop Analysis
Author(s): Rajagopalan S [Cypress Semiconductors] |
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| TB3: Tutorial & User Papers |
User: A Novel Approach to Get Optimal Power Estimate for 45nm Large SOC Using PTPX
Author(s): Sreekanth Madhava, Shibashish Patel, Biswajit Patra, Rangan Srinivasa [Qualcomm] |
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User: Enabling Accurate Timing Budget Parameter Measurements for DDR Critical Paths (1st Place - Best Paper; IC Design: Signoff)
Author(s): Vidit Babbar [Texas Instruments] |
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User: Want to Use UPF Based Flow, But Not Yet Ready. So, What to Do?
Author(s): Rangarajan Srinivasan, Ulhas Kotha [NVIDIA], Anantha Bhat [Synopsys] |
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| TC1: Tutorial & User Papers |
User: Improving Productivity of Synthesis and P&R with Synopsys Physical Guidance
Author(s): Girish T P, Nishant Gaidhani [AMD], George Jacob [Synopsys] |
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User: Low Power Optimization Techniques for Datapath Designs
Author(s): Vadivel Ramalingam, Srivatsa Srinath [Intel] |
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| TC2: User Papers |
User: Floorplanning in DCT for Improved QOR: A User Case Study
Author(s): Suresh Raman [Xilinx], Ramakrishna R [Synopsys] |
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User: Managing Test Requirements of Complex Scan Designs Using Synopsys Tetramax®’s Scan Compression Groups and Atomic Clocking
Author(s): HV Sanjay Krishna, Prashant Kulkarni, Srivaths Ravi [Texas Instruments], Mohammed Hussain [Synopsys] |
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User: Project Cycle-Time Reduction with ATPG Pattern Reusage
Author(s): Jasmer Singh, Rudraksha Dani [ST Microelectronics], Hardik Bhagat [Synopsys] |
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| TC3: Tutorial & User Papers |
User: Launch-Off Extra Shift (LOES) Transition Fault ATPG Methodology (1st Place - Best Paper; IC Design: Synthesis & Test)
Author(s): Milan Shetty, Swathi G, Rubin A. Parekhji [Texas Instruments] |
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User: Power-Aware Synthesis Flow with Design Compiler Using UPF 2.0
Author(s): Pawan Kumar Pandey, Girish T P, Vikram Kuralla [AMD] |