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| User Papers and Presentations |
| Physical Design and Sign-off |
An Experimental Study between ASIC Routing and Via-Configurable Routing
Author(s): Prashant Sharma, Karthik Natarajan [LSI Logic India Pvt Ltd] |
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Complexities in Timing Analysis - Managing Uncertainty
Author(s): Nitin Srimal [Sasken Communications] |
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Design of Ultra Low Power SRAM (1st Place - Best Paper)
Author(s): Vivek Nautiyal, Ashok Mishra [ARM Ltd] |
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Evaluating the Accuracy and Requirements of a Sign-off Crosstalk Noise Analysis Tool (1st Place - Best Paper)
Author(s): Prashant Soraiyur, Vivek Seth [Texas Instruments Pvt Ltd] |
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Improving Quality and Development Time of Standard Cell Libraries with Cadabra
Author(s): Murali Sundaram, Neethan Chikkanna, Anupama Soni, Adhip Kumar Patgar [Infineon Technologies India Pvt Ltd] |
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QoR Benchmark with ICC & PC on 65nm Design
Author(s): Ananth Somayaji, Amit Jain [Texas Instruments Pvt Ltd] |
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Reliability Issues - Electromigration / IR Drop Analysis using PrimeRail
Author(s): Amit Sharma, Ashish Rajput [STMicroelectronics] |
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Solving Transition, Capacitance, Crosstalk, Setup & Hold Violations Efficiently PT-SI Environment
Author(s): Chakradhar Tallury, Pradeep Kumar [Open-Silicon Research Pvt Ltd] |
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Timing Aware Metal Pattern Fill Using Hercules
Author(s): Vijay S Patri, Veerakumar Pitchiah [Intel Corp] |
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| Poster Session |
Assertion Based Verification Methodology
Author(s): Shailesh Dave [eInfochips Ltd.] |
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ETM Creation and Validation Methodology for Analog Cores
Author(s): Ravindran PN, Mallikarjun D [Cypress Semiconductor] |
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Standard Cell Leakage Power Characterization at Various PVT Corners using HSPICE
Author(s): Murali Rajagopalan, Kapil Kothari [Open-Silicon Research Private Limited] |
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| Synthesis and Test |
A Novel Method to Reduce Test Time using DFT Compiler MAX (1st Place - Best Paper)
Author(s): Srinivasulu Alampally, Jais Abraham [Texas Instruments Pvt Ltd] |
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A TCL Based Functional Auto ECO Flow
Author(s): Budumuru Vijay Kumar [Agere Systems] |
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DFT for Mixed-Signal ASIC
Author(s): Jovin Basil Roy J, Sharath Y [Tata Elxsi Ltd], Erik Nilson Comparini [AMI Semiconductor, Inc] |
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Enhanced Gate-Level Clock Domain Crossing Analysis using PT/DC
Author(s): Kannan Ramaswamy [Genesis Microchip] |
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Fault Simulation of Non-Scan Designs with Delays
Author(s): Y Sudheer Reddy [Tata Elxsi Ltd], Erik Nilson Comparini [AMI Semiconductor, Inc] |
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Improving Transition Fault Coverage Through the Identification of Redundant Transition Faults
Author(s): Sandeep Jain, Jais Abraham [Texas Instruments Pvt Ltd] |
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Power Aware Synthesis Strategies to Get Best QoR for a Multimillion Power Complex SoC
Author(s): Debajani Majhi, Denis Arias [Texas Instruments Pvt Ltd] |
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Simpler Diagnosis of Deterministic BIST Company
Author(s): Jais Abraham, Sandeep Jain, CP Ravikumar [Texas Instruments Pvt Ltd], David Buyze, Edwin Silveira, Sumitha Krishnamurthy [Synopsys, Inc.] |
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Test Pattern Compression for a 90nm, 128MHz SoC using DFT Compiler MAX
Author(s): Sandesh Prabhakar, Deepak Baranwal, Marco Casarsa [STMicroelectronics] |
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| Verification |
Anatomy of Reusable Verification IP in VMM World
Author(s): Desikan Srinivasan, Neeraj Chandak [Transwitch Corp] |
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Configuration Coverage Model 'Automation' in Functional Coverage
Author(s): Venu Pakalapaty [Qualcomm Bangalore Design Centre] |
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GUI Based Complex SoC Verification Environment using TCP/IP Socket
Author(s): Veena S Chakravarthi, Dinesh A [Centillium Communications Ltd] |
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Hitting Bugs through Assertions in Memory Controller (1st Place - Best Paper)
Author(s): Siddesh Math [Qualcomm] |
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Model-Design Verification using ESP-CV
Author(s): Mahendra Singh, Mukesh Chopra, Abhishek Bansai [STMicroelectronics] |
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RTL Coding Technique for Better Coverage
Author(s): Eswar S Vadlamani, Chaitanya K [Cypress] |
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SoC Verification: Challenges & Solutions using SystemVerilog
Author(s): Sanjay Budholiya, Sachin Nagar, Manish Kumar [Avago Technologies India Pvt Ltd] |
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Vera Based - Configurable Verification Environment for Reconfigurable VLIW Processors
Author(s): Subrahmanya Bharathi A [Qualcomm] |
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Verification of a Highly Configurable IP
Author(s): Vidhya Thyagarajan [Rambus Inc] |