|
| User Papers and Presentations |
| Design and IP Track |
A Parametrizable Approach to IP Re-use
Author(s): Janardan Prasad, Nilesh Acharya, Prasoon Kumar [Texas Instruments] |
|
Hierarchical Control FSMs to Enhance Control Path Coverage
Author(s): Sathyanarayan Balaji [Ittiam Systems Pvt Ltd] |
|
Integration Methodology with Reusable and Configurable IPs
Author(s): Preeti Rani, Sanjeev Varshney [STMicroelectronics], Vivek Singh, Sal Tiralongo [Synopsys Professional Services] |
|
Synthesis Friendly Design of Array of FIFOs
Author(s): Gopalakrishnan P K, Unnikrishnan [Cypress Semiconductor] |
|
Test Benches - The Often Ignored Element in IP Re-use
Author(s): Sarvesh Renade [Wipro Technologies] |
|
| Implementation Track |
Analysis Techniques for TI's Power Management Designs in 65nm Era
Author(s): Kalpesh Shah, Subhendu Kundu, Shitanshu Tiwari, Shailendra Dhuri, Roopesh Chandar, V Visvanathan, KA Rajagopal [Texas Instruments, India] |
|
Crosstalk Prevention, Repair and Pessimism Removal Techniques
Author(s): Vishal Srivastava, Deepti Khurana, Deepak Kumar Arora, Jwalant Joshipura [ST Microelectronics] |
|
DFT Methodology
Author(s): Pankaj Singh [Infineon Technologies] |
|
Flexible ECO Methodology using Gate-Array like ECO Cells
Author(s): Vishal Sharma [Sage Design Systems] |
|
Hierarchical Physical Design of 6.95M gate 0.18u Digital TV Display Chip
Author(s): Rajashree Srinidhi, Saidulu Palvai [NatSem India Designs Pvt. Ltd.] |
|
Power Domain Isolation Challenges and Techniques on a Complex SoC
Author(s): Paresh Joshi, Hetul Sanghvi, Naveen Gopalakrishna, Saravanan Karunavel [Texas Instruments India Pvt. Ltd.] |
|
Rapid JTAG and Boundary Scan Development using BSD Compiler
Author(s): Gopalakrishnan P K, Srihari P Babu [Cypress Semiconductor] |
|
Synthesis Challenges and Techniques on a Complex SoC
Author(s): Naveen Gopalakrishna, Paresh Joshi, Soujanna Sarkar [Texas Instruments, India] |
|
| Industry Panel |
Can India Drive the Next Paradigm Shift in VLSI Design Methodology?
Author(s): Dr. S.S. Mahant-Shetti, Dr. Satya Gupta, Dr. Sunil Sherlekar, Dr. Karthik.S and Prof. H.S. Jamadagni (Moderated by Dr. Mahesh Mehendale) |
|
| Verification Track |
DSP Verification Strategies using Vera
Author(s): R.Lavanya, Sivakumar, Najath Azeez, Sreejith [ Analog Devices] |
|
Formal Verification of a SoC Design Using Formality: Issues, Proposed Solutions and Wish List
Author(s): Avinash K R, Naveen S, Salil Malshe, Tapan Rath [Wipro Technologies] |
|
Gate Level Power Estimation Flow Features based on PrimePower
Author(s): Vinod Gupta, Kalpesh Shah [Texas Instruments India Pvt. Ltd.] |
|
Improving Verification Productivity for a Digital Signal Processor with Magellan
Author(s): Arvind Kaushik, Santosh Salunkhe, Sourav Roy, Tushar Ringe [Analog Devices] |
|
Mixed Signal Verification Methodology using Nanosim-VCS
Author(s): Sandeep Asija, Ritesh Jain, Ganesan Narayanan [Freescale Semiconductors] |
|
Random Verification of a Baseband Module using Vera
Author(s): Venkatagiri Chandrasekaran, Sunil Kakkar [Freescale Semiconductors] |
|
Scoreboard Directed Dynamic Constraint Modification for Higher Simulation Coverage
Author(s): Bhaskar Pal, Anindyasundar Nandi, Sayak Ray, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti [Indian Institute of Technology] |