SNUG India 2004 Proceedings

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User Papers and Presentations
General Session
Timing Optimization and Design Closure for a Silicon Revision
Author(s): Sharath Chandra L, Madhu Rao B G [Texas Instruments]
PaperPresentation

Implementation Session
Experiences with DBIST Implementation on a Large SOC Design
Author(s): Sandeep Jain, Jais Abraham, Rubin Parekhji [Texas Instruments]
PaperPresentation

IP2SS SDC Promotion
Author(s): Saurabh Shrivastava [STMicroelectronics, Noida (India)]
PaperPresentation

Methodology for Incorporating AVS/TS in SoC Designs
Author(s): Amit Das, Alok Anand, Shyam Prasad, Ganapathi Hegde, Purnabha Majumder [Natinal Semiconductor India Design Center]
PaperPresentation

R&D Panel
DSM Challenges in Designing SoCs
Author(s): Industry Experts
Presentation

Verification Session
Constrained Random Test Generator in an Automated Random Verification Environment: A Case Study
Author(s): Deepali S Maydeo [NitAl Computer Systems]
PaperPresentation

Design Issues for Assertion-Based Verification IPs: The OVA Experience
Author(s): Ansuman Banerjee, Bhaskar Pal, Pallab Dasgupta, P P Chakrabanti [IIT Kharagpur] Mithilesh Jha, Eduard Cerny [Synopsys, Inc]
PaperPresentation

OOPs Based VERA Framework For Effective Verification
Author(s): Jasleena Chhabra, Avneet Bhatia [Wipro Technologies]
PaperPresentation

State Machine Coding Styles and VCM
Author(s): Rohit Kumar [Sun Microsystems]
PaperPresentation

Validation of Verification Tools and Flows: An Analytical Approach
Author(s): Dibyendu Goswami, Swami Gangadharan, Vijay Patri [Intel]
PaperPresentation