SNUG Germany 2013 Proceedings

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User Papers and Presentations
A1 - Front-End Implementation - Advanced Synthesis
Applying Synopsys Physical Guidance (SPG) Methodology to Address Complex 28nm Design Challenges (1st Place - Best Paper)
Author(s): Jürgen Dirks - LSI
PaperPresentation

A2 - Backend Implementation - Advanced Applications
Achieving Timing Convergence by Resolving Congestion and Improving Clock Skew
Author(s):
PaperPresentation

Analog Net Routing with IC Compiler Custom Co-Design Flow
Author(s): Johannes Brücker - Renesas Electronics Europe
PaperPresentation

Resolving the Double Trouble in 20nm Place and Route
Author(s): Ulrich Hensel, Rainer Mann, Steffen Seeling - GLOBALFOUNDRIES, Jens Peters - Synopsys GmbH
PaperPresentation

A3 - System Design - Architecture Analysis
High-Level Power Modeling with Synopsys Platform Architect - A Signal Processing Use-Case (Technical Committee Award Honorable Mention)
Author(s): Bernhard Fischer, Christian Cech - Siemens
PaperPresentation

Power Modelling of 3D-Stacked Memories with TLM2.0-based Virtual Platforms
Author(s): Matthias Jung, Norbert Wehn, Christian Weis, Patrick Bertram - University of Kaiserslautern, Gunnar Braun - Synopsys GmbH
PaperPresentation

A4 - Analog Mixed-Signal Verification
An Accurate Path Verification to Secure and to Speed up Nanometer Design Closure
Author(s): Salvatore Santapà, Alessandro Valerio, Pierluigi Daglio - STMicroelectronics, Andrea Barletta - Politecnico of Milan, Massimo Prando - Synopsys
PaperPresentation

Circuit Check Extension to Optimize ERC Flow, User Experience and Guidelines for Expert and Novice Users
Author(s): Alessandro Valerio, Salvatore Santapà, Pierluigi Daglio STMicroelectronics, Italy, Carlo Borromeo - Synopsys, Italy, Chi-Tzung Wang - Synopsys, Taiwan
PaperPresentation

Enabling XA for Spectre-based Process Design Kits: a Look at Modeling Qualification
Author(s): Simone Locci, Klaus-Willi Pieper - Infineon Technologies AG
PaperPresentation

A5 - Digital Verification
Making the most of SystemVerilog and UVM: Hints and Tips for New Users
Author(s): Dr. David Long - Doulos
PaperPresentation

B1 - Implementation - Low Power
Improved Methodology for Leakage Optimization in Synopsys Tools
Author(s): Jürgen Karmann, Ravikumar Rajendraprasad - Infineon Technologies AG
PaperPresentation

Low-Power Verification using Power State Table Coverage
Author(s): Christophe Lamard, Jean Marie Guillermin - ST Microelectronics, François Cerisier, Mathieu Maisonneuve - Test and Verification Solutions, France
PaperPresentation

B2 - Implementation - Signoff
Double Patterning. Something to Worry about in Parasitic Extraction?
Author(s): Hendrik T. Mau - GLOBALFOUNDRIES
PaperPresentation

Qualification of Setup/Hold Time Calculation in PT 2012.06 without Delta Transition
Author(s): Sönke Grimpen - Infineon
PaperPresentation

Static Noise Analysis Including Power Noise (2nd Place - Best Paper)
Author(s): Sönke Grimpen - Infineon
PaperPresentation

B3 - System Design - Virtual Prototyping
Next-Generation Prototyping - a Hybrid Approach (3rd Place - Best Paper)
Author(s): Peter Blöcher, Uwe Grüner - ST-Ericsson
PaperPresentation

Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures
Author(s): Srinivas Boppu, Vahid Lari, Frank Hannig, Jürgen Teich - University of Erlangen-Nuremberg
PaperPresentation

B4 - Analog Mixed-Signal Verification
The Art of Reliability: Guidelines to Reduce IR-drop and Electro-migration Effects in Full Custom Designs
Author(s): Paolo Valente, Alessandro Valerio - STMicroelectronics, Claudio Rallo - Synopsys
PaperPresentation

B5 - New Technology - Verification Springsoft
Certitude and VCS at Module-level: a User's Experience (Technical Committee Award)
Author(s): Stephanie Legeleux, Andreas Pachl, Rafael Pena Bello - Freescale Semiconductor
PaperPresentation

Get Certitude About Your Tapeout Quality
Author(s): Joachim Geishauser, Alexander Schilling, Stephan Ruettiger - Freescale Halbleiter Deutschland GmbH
PaperPresentation

C1 - Implementation - Test
DFT and ATPG for Mixed 2-phase Latch and Edge Triggered Flop-based Designs
Author(s): Richard Illman - Dialog Semiconductor
PaperPresentation

C4 - Full Custom Design
Moving from Virtuoso to Synopsys Custom Designer
Author(s): Gernot Koch, Erich Gottlieb, Jonathan Bradford, Thomas Dilling, David Small - Micronas GmbH
PaperPresentation

C5 - IP - Implementation & Verification
FPGA-based Emulation of an Ultra Low-Power SoC
Author(s): Martin Gut - Texas Instruments
PaperPresentation

High-Speed Interface IP Selection, Module Level, and Chip Top Level Verification
Author(s): Andreas Vielhaber - Synopsys GmbH
PaperPresentation

C6 - Design Flow - Lynx Design System
Using the Lynx Design System to Minimize the SoC Implementation Effort and Cost
Author(s): Simone Borri, Pierre-Marie Signe, Christian Eichrodt - Abilis Systems, Riccardo Giordani - Synopsys GmbH
PaperPresentation

Tutorials
A1 - Front-End Implementation - Advanced Synthesis
Formality 2013.03 Update and Hierarchical UPF Flow
Author(s): David Low - Synopsys
Tutorial

A5 - Digital Verification
VCS Technologies for Best Debug and Analysis
Author(s): Werner Kerscher - Synopsys
Tutorial

A6 - Vision Session - High-Performance Core Implementation
Design with FinFET
Author(s): Marco Casale-Rossi - Synopsys
Tutorial

Engineering Trade-Offs in the Implementation of a High-Performance ARM® Cortex™-A15 Dual Core Processor
Author(s): Joe Walston - Synopsys, Inc.
Tutorial

B1 - Implementation - Low Power
Meeting Quality Goals for Gigascale Designs Trends and Solutions Part 1
Author(s): Nikolaus Mittermaier - Synopsys
Tutorial

B3 - System Design - Virtual Prototyping
Introduction to Hybrid Protoyping
Author(s): Philipp Jacobsohn - Synopsys GmbH
Tutorial

B4 - Analog Mixed-Signal Verification
Analog and Mixed-signal Verification Methodology Using Verilog-AMS
Author(s): Peter Thompson - Synopsys
Tutorial

Transistor Level Static Circuit Analysis to Tackle ERC & ESD Challenges
Author(s): Uwe Trautner - Synopsys GmbH
Tutorial

B5 - New Technology - Verification Springsoft
Introduction to Verdi³ Automated Debug System
Author(s): Jens Dickel - Synopsys GmbH
Tutorial

B6 - Vision Session: High-end Implementation Trends
Emerging Node Challenges and Opportunities
Author(s): Thomas Andersen - Synopsys
Tutorial

Power-Centric Timing Optimization Flow for an ARM® Cortex™-A7 Quad Core Processor
Author(s): Dale Lomelino - Synopsys, Inc.
Tutorial

C1 - Implementation - Test
Meeting Quality Goals for Gigascale Designs: Trends and Solutions
Author(s): Nikolaus Mittermaier - Synopsys GmbH
Tutorial

C2 - Implementation - Advanced ICC Features and Methodologies
Clockgating and Concurrent Clock & Data Optimization in IC Compiler for Improved Timing Closure
Author(s): Frank De Meersman - Synopsys
Tutorial

C3 - System Design - Prototyping & HLS
Model-based Design with Synphony MC High-Level Synthesis
Author(s): Philipp Jacobsohn - Synopsys GmbH
Tutorial

C4 - Full Custom Design
Laker Custom Layout Solution: An Advanced Process Node Custom Layout Tutorial
Author(s): Uri Golan - Synopsys Israel
Tutorial

C6 - Design Flow - Lynx Design System
Improve Design Quality with Efficient Design Exploration in Lynx Design System
Author(s): Riccardo Giordani, Chris Smith - Synopsys
Tutorial

Demo
A3 - System Design - Architecture Analysis
Low-Power Video Processing for the Mobile SoC: How Analysis of HW-SW Partitioning Gets the Most from Embedded GPUs
Author(s): Bart Vanthournout - Synopsys
Tutorial

C5 - IP - Implementation & Verification
Comprehensive System Validation of an Ultra-Low Power SoC with an FPGA-Based Emulation System
Author(s): Martin Gut - Texas Instruments, Laureano Carrasco - Synopsys