|
| User Papers and Presentations |
| A1 Tutorial & User Paper - Implementation: Synthesis |
Multi-Mode Multi-Corner Synthesis in Design Compiler - A Must or just Nice to Have? (2nd Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Bernhard Riess [Infineon Technologies AG] |
|
| A2 User Session - Implementation: Place & Route I |
Inserting and Integrating Level Shifters during Physical Implementation (ICC)
Author(s): Kousalya Nagakarthick, Ralph Sommer [LSI Logic GmbH] |
|
Mixed-Vth Leakage Optimization in the Final Design Stage - Experience with new Final-Stage Leakage Recovery Flow (3rd Place - Best Paper)
Author(s): Robert Häußler, Mihael Murković [Lantiq Deutschland GmbH], Anders Lind [Synopsys GmbH] |
|
Using Synopsys IC Compiler for DFM optimization at 28nm
Author(s): Rainer Mann, Ulrich Hensel, Vito Dai, Shobhit Malik [GLOBALFOUNDRIES], Jens Peters [Synopsys] |
|
| A3 Tutorial & User Paper - Verification & IP: Digital Verification |
Method for Reusable Low Power Mode Entry/Exit Verification Applied on Freescale S12 uC
Author(s): Joachim Geishauser, Alexander Schilling, Andreas Pachl [Freescale Halbleiter Deutschland GmbH] |
|
| A4 User Paper & Tutorial - AMS/Full Custom: AMS Verification I |
A Simple but Effective and High Accurate Parasitics Estimator for Prelayout Parasitic Estimation
Author(s): Hendrik Mau [GLOBALFOUNDRIES] |
|
| A5 User Session & Tutorial - System: High Level Synthesis & Verification |
Employing Synphony Model Compiler with Application Components for FPGA Processing Elements in Software Defined Radios
Author(s): Peter Troll [Rohde & Schwarz GmbH & Co. KG] |
|
Formal Verification and Validation of High-Level Optimizations of Arithmetic Datapath Blocks
Author(s): Theo Drane [Imagination Technologies Ltd.], Himanshu Jain [Synopsys, Inc.] |
|
| B1 User Session - Signoff: STA and Constraint Analysis |
Galaxy Constraints Analyzer Evaluation
Author(s): Sönke Grimpen [Infineon Technologies AG] |
|
Path-based Analysis : A Realistic Solution to Unrealistic Timing Paths in Complex ASICs (Technical Committee Award)
Author(s): Satinder Paul Singh, Farid Labib [LSI Corp. Germany] |
|
STA Fundamentals (1st Place - Best Paper)
Author(s): Sönke Grimpen [Infineon Technologies AG] |
|
| B3 Tutorial & User Session - Verification & IP: IP integration |
Chips and IPEAS - It’s not Mushy
Author(s): Jonathan Young [Synopsys Ltd.], Presenter: Steve Lloyd [Synopsys Ltd.] |
|
Evaluation of an on Chip Bus Fabric Solution Based on Synopsys IPs
Author(s): Bogdan Sbarcea [Siemens Romania], Majid Gameshlu [Siemens Austria], Andreas Vielhaber [Synopsys GmbH] |
|
| B5 User Paper & Tutorial - System: SoC Architecture Design |
Developing High-performance Wireless Systems by Combining Virtual Prototype Models
Author(s): Yvonne Gsottberger, Josef Eckmüller, Helmut Reinig [Intel Mobile Communications Germany] |
|
| B6 Combo Session - Automotive: Automotive System Design & Analysis |
Electrical Function & System Development of Commercial Vehicles at Volvo using Saber
Author(s): Samuel Alinder [Volvo Sweden] |
|
SABER Simulation of Electric Actuators
Author(s): Dr. Szabo, Dr. Moule [TRW Automotive Systems] |
|
Setting up an Enterprise-wide Automotive Model Library - Potentials, Requirements and Challenges
Author(s): Armin Schön [Continental Automotive Systems GmbH] |
|
| C1 Tutorial & User Session - Implementation: Low Power |
Hierarchical UPF Implementation and Verification
Author(s): Mario Orgis [Intel Mobile Communications Germany], Knut Dalkowski [Synopsys GmbH] |
|
| C2 User Paper & Tutorial/Demo Session - Test: Compression and Volume Diagnostics |
Improving DFTMAX Compression Results in Latch Based Designs
Author(s): Richard Illmann [Dialog Semiconductor] |
|
| C4 User Paper & Tutorial - AMS/Full Custom: Analog Implementation |
Deployment of Custom Designer for the 40nm Design Flow at Lantiq
Author(s): Michael Wagner, Johannes Rauh [Lantiq Deutschland GmbH], Oliver Bär [Synopsys GmbH] |
|
| C5 User Paper & Tutorial - FPGA: HW Assisted Verification |
FPGA-based Validation of TV Signal Demodulation Algorithms Using the Xilinx Virtex-6 based HAPS-62 Platform
Author(s): Rolf Nöthlings [Sony Deutschland GmbH] |
|
| C6 Combo Session - Automotive: Virtual Prototyping of HW/SW Systems |
Virtual Platform for a Chassis and Safety Application
Author(s): M. Thanner [Freescale] |