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| User Papers and Presentations |
| A1 - User session: Low-Power and Physical Aware Synthesis |
How Design Compiler Graphical Can Help Solve Floorplanning Issues (3rd Place - Best Paper)
Author(s): Laurent Besson [STEricsson] |
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Ultra Low Power REISC SoC Design Synthesis Flow using DC and UPF-Based Methodology
Author(s): Elio Guidetti, Giuseppe Notarangelo, Elena Salurso [STMicroelectronics] |
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UPF Front-End Experience on an Actual 45nm Design (2nd Place - Best Paper)
Author(s): Guilhem Caubit [ST-Ericsson] |
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| A2 - User and Tutorial: Low Power Verification |
Multi-Rail Hard Macro Modeling for Accurate Power Aware Simulation using MVSIM
Author(s): Mohit Jain, Rashna Seli [STMicroelectronics], Pierre-Yves Alla [Synopsys] |
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| A3 - User and Tutorial: Advanced Physical Design and Routing Technology |
Deploying ICC Zroute for Advanced Node Testchip Design
Author(s): Rainer Mann, Steffen Seeling, Ulrich Hensel [GLOBALFOUNDRIES] |
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Fast-Turn Physical Design Flow through the Adoption of Metal Programmable Technology
Author(s): Lorenzo Calì, Claudio Mucci, Valentina Nardone, Thierry Petit, Stefano Pucillo, Marco Scipioni, Stefania Stucchi [STMicroelectronics] Giuseppe Contarino [Synopsys] |
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| A4 - User session: Improving Yield and Test Quality |
Identification of Systematic Yield Issues using Volume Diagnostics - Case Study on a 45nm SoC
Author(s): Florent Garait, Stephane Lecomte, , Aymen Lamine, Roberto Gonella [STEricsson], Christophe Suzor [Synopsys] |
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LOES At-Speed Test Design with Transition ATPG
Author(s): Mohamed Al Ameri, Manu Baby [Dubai Circuit Design] |
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Test Points Insertion Flow to Improve Fault Coverage without Impacting Design Cycle
Author(s): Julien Pouget [STEricsson], Philippe Rossant [Synopsys] |
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| A5 - User and Tutorial: Rapid FPGA Prototyping |
Design Prototyping with CHIPit Systems for Space Applications
Author(s): Fabien Laborde [EADS Astrium] |
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| B1 - User Session: High-Level Synthesis, RTL Assembly and Constraint Checking |
Galaxy Constraint Analyzer: Filling the Gap in Timing Constraint Checking
Author(s): Philip Cuney [STMicroelectronics], Emmanuel Pluchart [Synopsys] |
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Getting Rid of SoC Assembly Bottleneck with coreAssembler
Author(s): Grégoire Coppey [STEricsson], Naresh Sharma [STMicroelectronics] |
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High-Level Design Methodology Using Synphony HLS
Author(s): Christine Masson [STMicroelectronics] |
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| B2 - User and Demo: Low Power Verification |
Leveraging Top-Level SystemVerilog Assertions for Power-Aware Verification
Author(s): Jerome Bombal, Fabien Camus [Texas Instruments] |
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MVRC Usage on a Complex Design from the RTL to the Low Power Signoff
Author(s): Frederic Saint-Preux [STEricsson] |
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| B3 - User and Tutorial: RTL to GDS Flow |
Timing Correlation between DCT and ICC for a High Performance STM32 Design
Author(s): Nathalie Meloux [STMicroelectronics] |
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| B4 - User session: Low Power ATPG and Advanced DFT Flows |
DFTMAX Low Pin Count: How to Save Test Cost in Device with Limited Pin Resource
Author(s): Paul Armagnat [STMicroelectronics] |
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Generating Low-Power ATPG Patterns using a Shift Power Budget (1st Place - Best Paper)
Author(s): Pascal BLANC [STEricsson], Saverio Graniello [STMicroelectronics], Philippe ROSSANT [Synopsys] |
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Hierarchical Adaptive Scan Synthesis and Core Wrappers Methodology Combined to Reduce Power During Scan Test (Technical Committee Award)
Author(s): Christophe Eychenne, Isabelle Delbaere, Caroline Carin [ST-Ericsson] |
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| B5 - User and Tutorial: Analog and Custom Design |
Custom Designer Advanced Scripting Capabilities
Author(s): Christophe Scarabello [Tiempo] |
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| C2 - User and Tutorial: Functional Verification and Virtual Platform |
Migrating to UVM: How and Why!
Author(s): Mike Bartley [Test and Verification Solutions] |
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| C3 - User and Tutorial: ICC In-design Techniques and PrimeTime ECO for Faster Sign-off Convergence |
ICC-IC Validator and ICC-PrimeRail New ‘In-Design’ Features: The ST/APG MSR 65nm) Testcase (Technical Committee Award Honorable Mention)
Author(s): Salvatore D'Argenio [STMicroelectronics], Giuseppe Contarino [Synopsys] |
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| C5 - User and Tutorial: AMS Simulation and Verification |
Hsimregnode to Drastically Improve Full Chip Simulation Performances
Author(s): Luca Buratti, Claudia Castelli, Pierluigi Daglio, Lorenzo Leone, Alessandro Valerio [STMicroelectronics], Luong Nguyen, Carlo Borromeo [Synopsys] |
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Metal Lines Parasitic Capacitances Extraction of Power DMOS Devices and Customization for Post-Layout Simulation
Author(s): Davide Cavalli [STMicroelectronics], Claudio Rallo [Synopsys] |