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| User Papers and Presentations |
| MA1 User - SystemVerilog & Improving Coverage with DFT Compiler |
Hijacking Flops for Fun and Profit (3rd Place - Best Paper)
Author(s): Martin Salomon [STMicroelectronics] |
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SystemVerilog for Design - Lessons Learned (A Practical Approach using Synopsys Tools)
Author(s): Ilian Tzvetanov [Exar Corp.] |
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| MA2 User - SystemVerilog & Low Power Verification |
A SystemVerilog Based ASIC DV Methodology (2nd Place - Best Paper)
Author(s): Botros Dalou, Abdelhalim El-Aboudi, Dennis Em, Karim Khordoc, Catherine Leung, Markus Pugi, Apurv Shah [Cisco Systems] |
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Benefits of Using MVSIMV-NLP for Low Power Verification
Author(s): Kendall Chan [Advanced Micro Devices, Inc.] |
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| MA4 User - Tips and Tricks for Leakage and Useful Skew |
Implementing Useful Skew Using Skew Groups
Author(s): Matthew Mei [Cisco Systems] |
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Tricks, Techniques and Assumptions - A Practical Guide to Low Leakage Implementation
Author(s): Richard Wieler, Dennis Lewis [Integrated Device Technology] |
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| MB1 User & Tutorial - AOCV Analysis with PrimeTime & Low-Power with DesignWare minPower |
Enabling Variation-Aware Timing Analysis using PrimeTime Cell-Specific AOCV Margining (Technical Committee Award)
Author(s): Khaled Heloue, Ed Bender, Rajit Seahra [Advanced Micro Devices, Inc.] |
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| MB3 User & Tutorial - Circuit Checks and Reliability Analysis |
Zapping Bugs in Analog Design with Topological Checks
Author(s): Denitza Tchoevska [Advanced Micro Devices, Inc.], Glen Hertz [Synopsys, Inc.] |
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| MB4 User - Advance Routing Techniques for DRC and ECO |
Minimum Metal ECO Routing Tips and Tricks (1st Place - Best Paper)
Author(s): Christopher Krueger [STMicroelectronics] |
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Zero DRCs Zroute Initiative
Author(s): Ilana Shternshain, Peter Churchill [Advanced Micro Devices, Inc.] |
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| MC4 User & Tutorial - Block Feasibility with ICC and 3D-IC |
Block Feasibility with ICC DP
Author(s): Danny Harutz, Nigasan Ragunathan [Cisco Systems} |