SNUG Boston 2012 Proceedings |
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| | User Papers and Presentations | | TA1 User & Tutorial Session: Verification - Debug Productivity | Simulation-Based Productivity Enhancements Using VCS Save/Restore
Author(s): Scot Hildebrandt, Lloyd Cha (Advanced Micro Devices); Vijay Akkaraju, Alok Sinha (Synopsys, Inc.) |
| | TA2 User Session: Methodology Solutions with Synopsys Physical Design Tools | Staged Physical Verification During Floorplanning to Ensure Predictable LVS Checking
Author(s): Frank Malgioglio (IBM); Kevin Brelsford (Synopsys, Inc.) |
| Targeting IBM’s 45nm SOI Process with IC Compiler (2nd Place - Best Paper)
Author(s): Nimit Nguansiri (The MITRE Corporation) |
| | TA3 User & Tutorial Session: Synthesis | An End-to-End Approach for Specifying and Verifying False and Multicycle Paths
Author(s): Bradley Dobbie, William Stysiack (Cavium, Inc.) |
| | TA4 User & Tutorial Session: Test | Multi-scan Compression Support in an AMD Core
Author(s): Thomas Clouqueur, Martin Amodeo (Advanced Micro Devices); Tim Yuan, Lori Schramm (Synopsys, Inc.) |
| | TA5 User Session: AMS Verification | Analog Mixed-Signal Verification Using UVM
Author(s): Warren Anderson, Shyam Sivakumar (Advanced Micro Devices); Vijay Akkaraju, Karim Aoua (Synopsys, Inc.) |
| Top-Level Electromigration and IR Drop Analysis of Mixed-Signal Blocks using CustomSim™ Reliability Analysis
Author(s): David Fritz, Ari Valero (LSI Corporation); Cheung Lam (Synopsys, Inc.) |
| | TB1 User & Tutorial Session: Verification - UVM | Implementing Reset Testing with UVM
Author(s): Timothy Kramer (The MITRE Corporation) |
| Transitioning to UVM from VMM
Author(s): Courtney Schmitt (Analog Devices) |
| | TB3 User Session: Top-Level Design Closure Using the Galaxy Platform | A Fast and Flexible Method of Full Chip Clock Planning for 32nm System on a Chip
Author(s): Khem Pokhrel, Avinash Rajah, Aleta Dozier, Justin Kernen, Ankit Shah (Intel) |
| Advanced Design Partitioning with IC Compiler Leveraging Physical Synthesis
Author(s): Jack Randall (Advanced Micro Devices) |
| Effective Top-down Usage from Design Planning to Tapein on 32nm SoC
Author(s): Khem Pokhrel, Keith Lyons, Stephen Gourlay, Anupama Subramaniam, Xufang Zhang, Aleta Dozier (Intel Corp.) |
| | TC1 User & Tutorial Session: Verification - Complex Designs | Assert Your Independence! Adopting the OVL Assertion Library as an IP/SoC Standard (3rd Place - Best Paper)
Author(s): John A. Thomson (Advanced Micro Devices) |
| | TC3 User Session: Physical Design - Advanced Clock Techniques in IC Compiler | Clocks Against Variation (1st Place - Best Paper)
Author(s): Gerard M. Blair (LSI Corporation) |
| Design and Analysis of a Conditional Clock Mesh
Author(s): Ranjith Hallur, Bill Stysiack (Cavium, Inc.) |
| | TC5 Tutorial & User Session: AMS Formal Verification | Exhaustive Equivalence Checking on ROM Macros
Author(s): Keerthi Chamakura (University of Texas at Dallas); Lindsey Tessier, Baosheng Wang (Advanced Micro Devices) |
| | Tutorials | | TA1 User & Tutorial Session: Verification - Debug Productivity | Using DVE for Exceptional Debug
Author(s): Daniel Grabowski (Oracle) |
| | TA3 User & Tutorial Session: Synthesis | Moving to Design Compiler 2012.06
Author(s): Janet Olson (Synopsys, Inc.) |
| | TA4 User & Tutorial Session: Test | Test Updates, Yield Improvement and the Influence of Standards
Author(s): Adam Cron (Synopsys, Inc.) |
| | TA6 Tutorial Session: FPGA - Co-Simulating with a Prototype System, Solving P&R Challenges on High-Density FPGAs | Simulation, Control and Design Interaction with FPGA-Based Prototyping Systems
Author(s): Peter Calabrese (Synopsys, Inc.) |
| Solving P&R Challenges on High-Density Xilinx FPGAs
Author(s): Brett Buma (Xilinx) |
| | TB1 User & Tutorial Session: Verification - UVM | UVM Past, Present, Future...
Author(s): Adiel Khan (Synopsys, Inc.) |
| | TB2 Tutorial & Vision Session: Solving Design Challenges at 28nm and Below | Achieving Design Success at 28nm and Below (Physical Design)
Author(s): Bill Sieredzki (Synopsys, Inc.) |
| Understanding the Source of 28nm and Below Design Challenges (Manufacturing)
Author(s): Jonathan White (Synopsys, Inc.) |
| | TB5 Tutorial Session: Custom Signoff | Using NanoTime on Complex Clock Designs of Memories and of Custom Digital Macros Part 1: Setup and Analysis of Complex Clocking Schemes in NanoTime Analyzing memories with complex clocking schemes in NanoTime Part 2: Analyzing memories with complex clo
Author(s): Norb Heindl (Synopsys, Inc.) |
| | TB6 Tutorial Session: FPGA - Synopsys Design Constraints in FPGA Space, High Reliability Techniques in Premier | High-Reliability Design Techniques in Synplify Premier
Author(s): Carl Cleaver, Meera Srinivasan (Synopsys, Inc.) |
| Using Synopsys Design Constraints (SDC) for FPGA
Author(s): Gene Stuckey (Synopsys, Inc.) |
| | TC1 User & Tutorial Session: Verification - Complex Designs | Discovery Verification IP for Advanced Protocol Checking and Debug
Author(s): Tushar Mattu (Synopsys, Inc.) |
| | TC2 Tutorial Session: Physical Design - IC Compiler 2012.06 Update and Top-Level Design Closure | Faster Top-Level Closure With Transparent Interface Optimization (TIO)
Author(s): Brad Ragazzo (Synopsys, Inc.) |
| Migrating to IC Compiler 2012.06: Release Update
Author(s): Dave Power (Synopsys, Inc.) |
| | TC4 Tutorial Session: PrimeTime and Constraints | Minimizing Risk in Multi-clock Designs with Galaxy Constraint Analyzer
Author(s): Mark DiGiovanni (Synopsys, Inc.) |
| Primetime/Primetime-SI 2011/2012 Special Topics and Methodology
Author(s): Robert Grozier (Synopsys, Inc.) |
| | TC5 Tutorial & User Session: AMS Formal Verification | ESP Memory Redundancy Verification
Author(s): Dave Hedges (Synopsys, Inc.) |
| | TC6 Tutorial Session: Flow Automation and Programmable Design - Lynx & Processor Designer | Designing Programmable Hardware Accelerators: Gaining Flexibility Without Compromising Power, Area and Performance
Author(s): Drew Taussig (Synopsys, Inc.) |
| Managing Power on Hierarchical Designs using UPF with Lynx Design System / Designing High-Performance ASICs with Lynx Design System
Author(s): Cyrille Thomas, Kristine Westland (Bull SAS) (Synopsys, Inc.) |
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