SNUG Boston 2011 Proceedings

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Complete Proceedings


User Papers and Presentations
TA1 User & Tutorial - Integrating UVM-SystemVerilog within a C/C++
Migrating from C++ to SystemVerilog: Anatomy of a Hybrid Testbench
Author(s): Brian R. Folsom [Cavium Networks]
PaperPresentation

TA3 Tutorial & User Session - DC Explorer and DC Physical Guidance
Improving Productivity of Synthesis and P&R with Synopsys Physical Guidance (SPG) Technology
Author(s): Girish TP, Nishant Gaidhani, Lahari Samineni, George Jacob [AMD India Engineering Centre Pvt. Ltd.]
PaperPresentation

TA4 User - Power Recovery and Power Rails
Late Stage Leakage Recovery using IC Compiler
Author(s): Jeff Shi [LSI Corp]. Cristian Golovanov [Synopsys, Inc.]
PaperPresentation

Power Rails, Standard Cell Libraries and Metal Stacks...Making the Right Choice
Author(s): Mike Young [Analog Devices, Inc.]
PaperPresentation Railsix.xlsx

TA6 User & Tutorial - HSPICE
The Impulse Response - "Fingerprint" for SERDES Channel Characterization (Technical Committee Award Honorable Mention)
Author(s): Johann Nittmann, Frank Corcoran [Cavium Networks]
PaperPresentation

TB1 User - Advanced VCS Verification Topics
Formal Verification and Validation of High-Level Optimizations of Arithmetic Datapath Blocks
Author(s): Theo Drane [Imagination Technologies Ltd.], Himanshu Jain [Synopsys, Inc.]
PaperPresentation

Improving Functional Gate Level Simulation Performance - A Case Study (3rd Place - Best Paper)
Author(s): Joe Tompkins [Cavium Networks], Prathamesh Joshi [Synopsys Inc.]
PaperPresentation

SystemVerilog Functional Co-Simulation
Author(s): Todd Honan, Stuart Patterson [Analog Devices, Inc], Paul Collins [Synopsys, Inc.]
PaperPresentationSession Recording

TB3 User & Tutorial - Low Power
Modeling State Dependent Internal Power of Cells and IP
Author(s):
PaperPresentation

Recovering Lost Power in a CPU Synthesis Flow
Author(s): Ethan Bancala, Darryl Prudich [Advanced Micro Devices], Vivek Santhosh [Georgia Institute of Technology]
PaperPresentation

TB4 Tutorial & User - ICC New Features and Custom Designer Interface
ICC-Custom Designer Link to Improve the Product Development Cycle Time!
Author(s): Christelle Leherpeur [STMicroelectronics]
PaperPresentation

TB5 User & Tutorial - Advanced Test Techniques
Block Level Scan Insertion and Layered Approach to Transition ATPG Vector Generation (1st Place - Best Paper)
Author(s): Zahi Abuhamdeh, Vincent D'Alessandro [Silicon DFx, Inc.], Ramon Zuniga, Wayne Fang [ClariPhy Communications, Inc.]
PaperPresentation

Power Aware Scan Insertion from a Non-Synopsys Entry Point
Author(s): Naveen Mysore [LSI Corp.]
PaperPresentation

TB6 Tutorial & User - Discovery AMS, XA and Custom Designer
Deployment of Full Custom Created Timing Shell Methodology to Hand-Off Macros from CD to ICC (2nd Place - Best Paper)
Author(s): Michael Wagner [Lantiq D GmbH], Oliver Baer, Kurt Haun [Synopsys GmbH]
PaperPresentation

TC4 User & Vision - Primetime Advanced Technology
Improving Delay Calculation Accuracy for 28nm Designs using PrimeTime GBA Waveform Analysis Techniques
Author(s): Lun Ye, Joe Jamann, Rich Laubhan [LSI Corp], Tom Wilderotter [Synopsys, Inc.]
Presentation

Tutorials
TA1 User & Tutorial - Integrating UVM-SystemVerilog within a C/C++
Using DPI to Facilitate Communications in a SystemVerilog - C/C++
Author(s): Nasib Naser [Synopsys, Inc.]
Tutorial

TA2 Tutorial - FPGA Synthesis
A Method for Implementing SystemVerilog Monitors on HAPS FPGA Platforms
Author(s): Pete Calabrese [Synopsys, Inc.]
Tutorial

Putting it All Back Together Again: An FPMM Excerpt
Author(s): Doug Amos [Synopsys, Inc.]

TA3 Tutorial & User Session - DC Explorer and DC Physical Guidance
Rapid Prototyping with DC Explorer
Author(s): Janet Olson, Danny Rawlings [Synopsys, Inc.]

TA5 Tutorial - StarRC
IC Validator - Intelligent Use of Hierarchy for High-Performance Layout-Versus-Schematic Flows
Author(s): Jamie Byrum [Synopsys, Inc.]
Tutorial

Resolving 28nm and Below Parasitic Extraction Challenges using StarRC
Author(s): Mani Woodroffe [Synopsys, Inc.]
Tutorial

TA6 User & Tutorial - HSPICE
HSPICE Release Update for 2011.09
Author(s): Bob Williams [Synopsys, Inc.]
Tutorial

TB2 Tutorial - Prototyping
Advanced Techniques for Design Analysis and Debug Using Synplify RTL/TECH Schematic Viewers with VCS Integrations
Author(s): Kris Dobecki [Synopsys, Inc.]
Tutorial

Welcome to the Machine - Techniques for Fault-Tolerant FSMs
Author(s): Carl Cleaver [Synopsys, Inc.]
Tutorial

Xilinx Team Based Design
Author(s): Brett Buma [Xilinx, Inc.]
Presentation

TB3 User & Tutorial - Low Power
Power Implementation Updates and Highlights
Author(s): John Geremia [Synopsys, Inc.]

TB4 Tutorial & User - ICC New Features and Custom Designer Interface
IC Compiler 2011.09 Pattern-Based Detection and Layer Assignments
Author(s): Chris Kennedy [Synopsys, Inc.]
Tutorial

Using IC Compiler New Feature preroute_focal_opt -layer_optimization to Improve Buffering Quality and Timing QoR
Author(s): Jerry Liu , Changge Qiao [Synopsys, Inc.]
Tutorial

TB6 Tutorial & User - Discovery AMS, XA and Custom Designer
CustomSim (XA & HSIM) & CustomExplorer Ultra Release Updates for 2011.09
Author(s): Luong Nguyen, Dwayne Holst [Synopsys, Inc.]
Tutorial

TC1 Tutorial - Reusable Verification IP
IP-XACT: A new IEEE standard for IP integration
Author(s): John Swanson [Synopsys, Inc.]

New Levels of Verification IP Productivity
Author(s): Bernie DeLay [Synopsys, Inc.]
Tutorial

TC2 Tutorial - FPGA Synthesis
FPGA Live Debug Using Synopsys Identify Tools
Author(s): Pete Calabrese, Kris Dobecki [Synopsys, Inc.]
Tutorial

Technical Review of New Capabilities in Synplify Pro / SynplifyPremier 2011.09
Author(s): Sara Steigerwald [Synopsys, Inc.]
Tutorial

TC3 User-torial & Tutorial Session - Lynx and Formality
Formality Updates and Verification Considerations in Design Compiler Based Flows
Author(s): Steve Lamb [Synopsys, Inc.]
Tutorial

Rapid Design Exploration with the Lynx Design System
Author(s): Stacy Frank [IDT], Kriss Westland [Synopsys, Inc.]
Presentation

TC5 Tutorial - Test
DFTMAX Compression, TetraMAX ATPG, STAR Memory System, and Yield Explorer: Accelerate Higher Quality, Lower Cost Test
Author(s): Adam Cron [Synopsys, Inc.]
Tutorial

TC6 Tutorial - Custom Design
Custom Editing Solution for IC Compiler Designs
Author(s): Ed Lechner, Denis Goinard [Synopsys, Inc.]

Synopsys 2011.09 Custom Design Solution Highlights
Author(s): Ed Lechner, Fredrik Ivarsson [Synopsys, Inc.]
Tutorial