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| User Papers and Presentations |
| MA1- RTL/SystemVerilog Coding Practices for Synthesis |
Building Polymorphic Modules with Synthesizable SystemVerilog Constructs
Author(s): Brian Hook [Analog Devices, Inc] |
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The Ten Commandments of RTL Coding
Author(s): Eric Ryherd [Cypress Semiconductor] |
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| MA2 - Advancements in Routing |
Improving Routing QoR, DFM and Runtime at 45nm with Zroute Technology in IC Compiler
Author(s): Sunil Mehta, Vladimir Yutsis [Advanced Micro Devices, Inc.], Linda Davidson, Frank C. Gover [Synopsys, Inc.] |
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| MA3 - Multi-Simulation Environments |
Porting Legacy Verification Environment to SystemVerilog Based Testbenches for Complex Optical Networking SoC
Author(s): Darshan Sheth, Nilesh Ranpura [eInfochips] |
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Using Cosimulation of MATLAB and Simulink with VCS in a Functional Verification Environment (Best First-Time Presenter)
Author(s): Eric Cigan, David Lidrbauch [The MathWorks, Inc.] |
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| MB1 - Easing Physical Design Challenges during Synthesis and Power Analysis |
A Systematic Analysis of the Correlation Between DC-T and ICC
Author(s): Vishwas Rao, J.C. Parker [LSI Corporation], Thomas Wilderotter [Synopsys, Inc.] |
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DC Graphical: The Promise and the Reality (Technical Committee Award Honorable Mention)
Author(s): Philip Watson [ARM, Ltd.], Tom Fairbairn [Synopsys, Inc.] |
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Hybrid Approach to Power Analysis
Author(s): Pankaj Aggarwal, Rashedul Islam [Tensilica Inc.] |
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| MB2 -Low Power and Hierarchical Implementation |
A User's Experience in Developing a Low Power Flow with UPF
Author(s): Colm O'Doherty, Alan Whooley, Brian Coffey [Analog Devices, Inc.] |
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A Utility for Leakage Power Recovery within PrimeTime-SI (Technical Committee Award Honorable Mention)
Author(s): Bruce Zahn [LSI Corporation] |
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| MB3 - Advanced Verification Special Topics |
Constraint Solver Diagnostics
Author(s): Henrik Scheuer [Advanced Micro Devices, Inc.], Alex Wakefield [Synopsys, Inc.] |
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Reducing Failing Testcase Length: Mixing Brute-Force and Intelligence to Extract Meaningful Information from Many Simulations (2nd Place - Best Paper)
Author(s): Jonathan Wolfe [MediaTek Wireless, Inc.] |
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Verifying a Challenging Processor Core Using Magellan
Author(s): Tushar Ringe [Analog Devices, Inc.] |
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| MB4 - AMS Simulation with HSPICE and HSIM |
HSIMplus CircuitCheck on Mixed-Signal Power-Management Designs: A Life-Saver
Author(s): Vincent Bligny [STMicroelectronics] |
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W-Element and S-Parameter Models for High Speed Board Traces - Do We Need Both?
Author(s): Johann Nittmann, Scott Meninger [Cavium Networks] |
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| MC3 - SystemVerilog Tips and Techniques |
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog (1st Place - Best Paper)
Author(s): Clifford Cummings [Sunburst Design, Inc.] |
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Just When You Thought It Was Safe to Start Coding Again... Return of the SystemVerilog Gotchas (3rd Place - Best Paper, Technical Committee Award)
Author(s): Shalom Bresticker [Intel Corporation] |
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| MC4 - User Experiences with XA |
Acceleration of Analog Simulations with Synopsys XA
Author(s): Larissa Nitchougovskaia [Advanced Micro Devices, Inc.] |
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XA Integration in Custom Power MOSFET Analysis Flow
Author(s): Giuseppe Greco [STMicroelectronics], Claudio Rallo [Synopsys, Inc.] |
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| TA1 - Test in the Modern World |
Case Study - Physical Impact of Scan and Compression
Author(s): Ralph Jankowich [Qualcomm], Howard Gainey, Brad MacMonagle [Synopsys, Inc.] |
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TetraMAX ATPG Power-Aware Results on the ARM Cortex™-A8 Microprocessor
Author(s): Frank Frederick, Teresa L. McLaurin [ARM Inc.] |
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User Experience with Small Delay Defect ATPG
Author(s): Zahi Abuhamdeh, Vincent D'Alessandro [TranSwitch Corporation], Mona Marmash [Synopsys, Inc.] |
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| TA2 - Physical Design/Sign Off |
Accurate Timing Closure with Voltage Aware STA
Author(s): Anil Gundurao, Ali Eltoukhy [Cypress Semiconductor] |
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Unintentional Forward Biased Diode Checker
Author(s): Arnold Baizley, Joe Iadanza [IBM Corporation] |
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| TA3 - VMM in Action |
Applying VMM to the Verification of an Industrial Control Design
Author(s): Iman Abdo, Ryan Yuan Chen [Patni Americas] |
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Dealing with Inexactitude in VMM Verification
Author(s): Joseph Manzella [LSI Corporation] |
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Verifying Designs for Wireless-Broadband Applications Using SystemVerilog and Next Generation VMM
Author(s): Heedo Jung [Samsung Electronics Co.], Aditya Kher [Synopsys, Inc.] |