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| User Papers and Presentations |
| MA1 - Low Power Implementation Techniques |
Power Optimization and Calculation with Power Compiler and PrimePower for SoC Designs
Author(s): Karsten Matt [AMD Saxony LLC & Co KG] |
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Stop that Leak! Augmenting your PC/Astro Flow with Multi-Vt and Direct MilkyWay Access
Author(s): Neel Das [Tallika Corporation] Ravi Ranjan [Conexant Systems, Inc] |
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Synthesis and Physical Synthesis Design Methodologies Using Multi-threshold Devices (Technical Committee Award)
Author(s): Maurice P. Kinney, Chris Kiegle [IBM Microelectronics] |
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| MA2 - Cost-Effective Testing Techniques for DSM Designs |
Efficient Scan Design Using DFT Compiler
Author(s): Harish Dangat [Cypress Semiconductor] |
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The Expanding Uses of At-Speed ATPG
Author(s): Christopher Tice [Intel Corporation] |
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| MA3 - SystemVerilog Offers New Design and Verification Paradigms |
Integrating SystemC Models with Verilog and SystemVerilog Models Using the SystemVerilog Direct Programming Interface
Author(s): Stuart Sutherland [Sutherland HDL, Inc] |
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Modeling FIFO Communication Channels Using SystemVerilog Interfaces
Author(s): Stuart Sutherland [Sutherland HDL, Inc] |
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SystemVerilog 2-State Simulation Performance and Verification Advantages
Author(s): Lionel Bening [Hewlett-Packard] Clifford E. Cummings [Sunburst Design, Inc] |
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| MB1 - Low Power Design Methodologies |
High-Level Power Characterization of the AMBA Bus Interconnect
Author(s): Andrea Bona, Marco Caldari, Vittorio Zaccaria, Roberto Zafalon [STMicroelectronics] |
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Implementing Power Management IP for Dynamic and Static Power Reduction in Configurable Microprocessors using the Galaxy Design Platform at 130nm (3rd Place - Best Paper)
Author(s): Dan Hillman [Virtual Silicon] John Wei [Tensilica] |
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Power Delivery — Topological Design Strategy and Implementation Tips
Author(s): Malcolm White [Corrent Corporation] |
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| MB2 - Design Closure |
Equivalency Checking - A Case Study
Author(s): Joe Manzella [Agere Systems] |
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Hold Time Fixing for Multimode Design
Author(s): Tony Chen, Jenny Gong, Yigang Sun [Qualcomm, Inc] |
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The Human ECO Compiler (1st Place - Best Paper)
Author(s): Steve Golson [Trilobyte Systems] |
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| MB3 - High Level Functional Verification |
Assertion Based Constraint Modeling of Layered Protocols in Magellan
Author(s): Abhinav Agrawal, Manoj Kumar T [Synopsys, Inc] |
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Creating an SoC Response Checker Without Breaking a Sweat
Author(s): Chi Duong [Freescale Semiconductor, Inc] Fraya H. Cohen [Synopsys, Inc] |
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| MC1 - RVM Based Verification |
Application of RVM for Vera On a Networking Design Case Study
Author(s): Cristian Samoila [CIENA Corporation] Jason C. Chen [Synopsys, Inc] |
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Building Reusable Verification IP Using Synopsys' Reference Verification Methodology
Author(s): Neil Johnson, Ian Perryman, Branko Petrovich, Christian Vasiliu [Altera Corporation] Hans van der Schoot [Design Verification Consultant] |
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Verifying the ST BusSwitch using Vera and RVM
Author(s): Remi Francard, Shashank Raj, Harpreet Singh [STMicroelectronics] Fabian Delguste [Synopsys, Inc] |
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| MC2 - Physical Verification and Analysis |
Automating Analog Verification in a Mixed-Mode Simulation (2nd Place - Best Paper)
Author(s): Michael Laramie [asicNorth] |
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Parasitic Extraction at 90nm and Beyond
Author(s): William Piper, Edward Seibert, Wayne Woods, Cole Zemke [IBM] |
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Yield Management and Incorporating Physical Design Data into Logical Simulations
Author(s): Jonathan Winslow [IBM] |
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| MC3 - Assertion Based Verification |
Assertion Recipe, From Theory to Practice
Author(s): Jackson Nichol [CIENA Corporation] Benjamin Chin [Synopsys, Inc] |
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SVA4T: SystemVerilog Assertions — Techniques, Tips, Tricks, and Traps
Author(s): Wolfgang Ecker, Volkan Esen, Thomas Kruse, Thomas Steininger [Infineon Technologies] Peter Jensen [Syosil Consulting] |
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| R&D Panels |
TB1 - Power Sign-off for 130 Nanometer Designs and Below
Author(s): Donald Friedberg [Agere Systems], Carl Holzwarth, Barry Pangrle, Pradeep Saraswat, Li-Pen Yuan [Synopsys, Inc.] |
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TB3 - Analog Mixed Signal Design
Author(s): Syam Veluri [Analog Devices], Dave Chou, Dave Cronauer, Keith Lanier, Warren Wong [Synopsys, Inc.] |
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TC5 - Getting Started with SystemVerilog for Design and Verification
Author(s): Clifford Cummings [Sunburst Design, Inc.], Tom Carlson, Surrendra Dudani, Joao Geada, Phil Moorby, Karen Pieper, Dave Rich, Arturu Salz [Synopsys, Inc.] |
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TD4 - Design Planning for the Real World
Author(s): Neeraj Kaul, Sufyan Khan, Philip Tai, Yung Wuu [Synopsys, Inc.] |