Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Overview Power management and low power design introduce a new assortment of bugs and failure mechanisms to IC designs. The task of verification, already a critical path to the delivery of the chip, now needs to take on additional tests and flows to ensure the power management scheme is functional.
The complexity of power management and the broad spectrum of design scenarios could easily lead to escaped bugs without a rigorous methodology in place. In this webinar, we focus first on the complexities and changes brought about in the low power era and the bug types that are new to low power design. We then cover the process of rigorous verification for low power and present a structured and reusable methodology for low power. The webinar highlights the VMM extensions to base classes for low power that can be quickly used to replicate an efficient verification environment for low power designs. All the concepts covered in this webinar are detailed in the recently published Verification Methodology Manual for Low Power (VMM-LP), which customers of Synopsys can download in a PDF form from the VMM Central Web site.
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