Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Overview The Discovery Visualization Environment (DVE) is a next-generation, full-featured debug and visualization environment within the VCS functional verification solution. DVE offers unified debug and analysis of Verilog, VHDL, C/C++/SystemC, SystemVerilog Assertion/Design/Testbench and analog waveform.
In this webinar, you will learn how the tight integration between the schematic, waveform and source windows can ease the debug of RTL. We cover the back tracing feature in DVE and discuss how it helps to locate the causes of contention in design. You will also hear about a number of additional advanced DVE features, including coverage, planning, and interactive debug of a VMM verification environment with SystemC. At the end of the webinar, our expert panelists provide a number of useful tips and tricks for advanced users of DVE then hold a lengthy, interactive Q&A session.
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