HOME    TOOLS    VERIFICATION    FUNCTIONAL VERIFICATION

The VCS Discovery Visualization Environment (DVE)

Overview
The Discovery Visualization Environment (DVE) is a next-generation, full-featured debug and visualization environment within the VCS functional verification solution. DVE offers unified debug and analysis of Verilog, VHDL, C/C++/SystemC, SystemVerilog Assertion/Design/Testbench and analog waveform.

In this webinar, you will learn how the tight integration between the schematic, waveform and source windows can ease the debug of RTL. We cover the back tracing feature in DVE and discuss how it helps to locate the causes of contention in design. You will also hear about a number of additional advanced DVE features, including coverage, planning, and interactive debug of a VMM verification environment with SystemC. At the end of the webinar, our expert panelists provide a number of useful tips and tricks for advanced users of DVE then hold a lengthy, interactive Q&A session.

To view the webinar, please complete this form and click on the "continue >>" button below.

Required Required Fields

Business Email:Required
First Name:Required
Last Name:Required
Phone:Optional
Job Title:Required
Company:Required
Division:Optional


Verification Code:Required Verification Code (What is this?)