Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Overview Synopsys® VIP for OCP includes support for OCP 3.0, 2.2, 2.2 and 2.0 versions of the OCP specification including cache coherence. It enables the verification of master and slave devices, and OCP based fabrics. It provides 100% coverage as defined in the OCP specification. The Synopsys VIP for OCP is endorsed by OCP-IP and is included in the CoreCreator verification suite provided to members of the OCP-IP organization. Synopsys VIP for OCP is integrated with the Synopsys VIP Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, graphical view of complex and highly interleaved traffic.
Please complete the following form then click 'continue >>' to complete the download. Note: By registering, you acknowledge and agree to the terms of the Synopsys Privacy Policy.