Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Overview The Synopsys Non-Volatile Memory Express (NVMe) VIP is designed to help thoroughly verify NVMe designs using both random and directed simulation. The NVMe verification IP (VIP) adds an application interface to the Synopsys PCI Express VIP. The NVMe VIP requires the Synopsys PCI Express SVC. The VIP is implemented to be verification methodology neutral, and can be integrated with and controlled by any hardware verification language such as SystemVerilog (including UVM), C/C++, and Verilog. It runs on all popular simulators.
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