Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Overview Synopsys® Verification IP (VIP) for AMBA® AHB™ and APB3™ provides complete support for AHB and APB interfaces including all data widths, address widths, AMBA-LITE and multi-layer AHB. With its comprehensive protocol, methodology, verification and ease-of-use features, users are able to achieve rapid verification coverage closure of their AMBA-based designs.
Protocol
Interfaces
Methodologies
Simulators
AMBA AHB, APB
AHB 2.0, AHB-Lite, Multi Layer AHB, APB3
UVM, VMM, Verilog
VCS, Questa, IUS
Please complete the following form then click 'continue >>' to complete the download. Note: By registering, you acknowledge and agree to the terms of the Synopsys Privacy Policy.
