HOME    TOOLS    VERIFICATION    FUNCTIONAL VERIFICATION    VERIFICATION IP

Datasheet Download

Synopsys Verification IP for SATA

The Serial ATA (SATA) System Verification Component (SVC) is designed to verify SATA-based designs using both random and directed simulation. The SATA SVC supports constrained randomization parameters throughout the layers to aid in achieving coverage during verification. The SVC is verification methodology neutral, and can be integrated with and controlled by any hardwre verification language (e.g. SystemVerilog, UVM, C / C++, Vera, Specman, or Verilog). The SATA SVC supports all major simulators.

Please complete the following form then click 'continue >>' to complete the download.   Note: By registering, you acknowledge and agree to the terms of the Synopsys Privacy Policy.

Required Required Fields

Business Email:Required
First Name:Required
Last Name:Required
Phone:Required
Job Title:Required
Company:Required
Country:Required
Address:Required
City:Required
State/Province:
Optional
Postal/Zip Code:Required



(requires browser cookies to be enabled)