Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Synopsys Test SIG Event at ITC 2012 Accelerate Time-to-Quality
Thank you for your interest in the Test SIG at ITC 2012. Please complete this brief survey to register. (Your answers and information will remain confidential.)
Shortly after submitting the form, you will receive an email confirmation for your records. We look forward to seeing you at the event!
1. Which of the following best describes your activities?
DFT implementation
CAD/software development
Test program development
Test methodology/architecture
Yield engineering and failure analysis
Other
2. Which of the following best describes your role?
Individual contributor
Manager
Consultant or Contractor
Academic
Other
3. If you use compression, what is the typical number of scan inputs per CODEC for testing your designs? (Select the CLOSEST from the following)
1 scanin pin
2-3 scanin pins
4-7 scanin pins
8-32 scanin pins
>32 scanin pins
I don't know
N/A
4. If your designs use DFTMAX, do you use Serializer for pin-limited test?
Yes
No
I don't know
N/A
5. What is the maximum operating frequency of your tester(s) for scan data? (Select the CLOSEST from the following)
<10 MHz
10-49 MHz
50-100 MHz
>100 MHz
I don't know.
N/A
6. What is your typical internal scan shift frequency? (Select the CLOSEST from the following)
<10 MHz
10-49 MHz
50-100 MHz
>100 MHz
I don't know
N/A
7. Which fault models do you use today and in your next design? (Check all that apply)
Next Design
IDDQ
Transition delay
Small delay defect
Path delay
Bridging
N-Detect
Gate exhaustive
8. Which methodologies do you use today and in your next design? (Check all that apply)
Today
3D-IC design
IEEE 1500 core-based test
IEEE P1687
In-system self-test
Speed binning
Power-aware ATPG
Power domain-based ATPG
Test points (control/observe)
Volume diagnostics
Next Design
3D-IC design
IEEE 1500 core-based test
IEEE P1687
In-system self-test
Speed binning
Power-aware ATPG
Power domain-based ATPG
Test points (control/observe)
Volume diagnostics
9. For each test capability, which vendor solution do you use most often? (Choose only ONE vendor for each capability)
Cadence
Mentor
Synopsys
In-house
Other
N/A
10. For the test capabilities you require, please indicate how much improvement is needed: (1 - Least improvement needed, 5 - Most improvement needed.)
1
2
3
4
5
11. If you have additional comments, please add them here:
Please enter the verification code shown below: (What is this?)
