Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
In this special 2011 IEDM edition of TCAD News, we present two articles which are highly relevant to advanced logic and memory technologies. The first article discusses a recently developed Impedance Field Methodology (IFM) for analyzing the impact of random variability on device performance. The second article covers the 3-D simulation of FinFET devices, including the analysis of doping and stress proximity effects.
Required Fields
