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TSMC Advantages
TSMC (Taiwan Semiconductor Manufacturing Company) is located in the Hsin-Chu Science-Based Industrial Park in what is referred to as Taiwan's "Silicon Valley." The company is listed on the Taiwan Stock Exchange (TSE) and on the New York Stock Exchange (NYSE) under the trading symbol of TSM.

It is not by chance that TSMC is the world's largest and most successful dedicated independent semiconductor foundry . It is by plan and by charter. As the first "pure play" foundry company, we have experienced strong growth by being a true partner with our customers and by not competing against them by designing and manufacturing our own brand of IC products.

Companies from around the world have trusted TSMC with their integrated circuit manufacturing needs for over 16 years (we were founded in 1987) and we continue to work hard at earning that trust every day.

The evolution of advanced IC technology over the past decade has been so rapid that it has changed the way that all companies do business. Demands for faster design cycles have increased. Demands for faster time-to-market have increased. Demands for higher speeds and product quality have increased as well. These are some of the many reasons companies turn to TSMC as their manufacturing partner.

In addition to the foundry service, TSMC also provides comprehensive customer-oriented design services through the collaboration between our own design service team and 3rd party Design Service Alliance members. To facilitate streamlined IC design execution, TSMC’s design service offerings includes Technology Kits , Libraries, IPs, Reference Flows, Design Implementation Services, and IC Validation (Silicon Debug and Repair).

TSMC Reference Flow


	Foundry Industry's Leading Reference Flow Features Unique Advances in Power Management through Methodology and Library Integration Power Building upon the company's pioneering Power Closure methodology in Reference Flow 5.0, Reference Flow 6.0 drives power consumption down even further with an advanced methodology and seamlessly integrated low-power libraries targeting TSMC's advanced low power processes. Reference Flow 6.0 provides new voltage scaling capability supporting multiple voltage islands which gives the designers the full flexibility to take advantage of the full range of dynamic power saving opportunities. In addition, Reference Flow 6.0 features a unique power gating technology utilizing the multi-threshold CMOS (MTCMOS) design structure to mitigate leakage power. By inserting high Vt footers to shut down the circuits that are not operating, designers can cut the leakage by 90 percent or more, depending on the implementation being used. TSMC is offering the fine-grained MTCMOS technology initially, with the coarse-grained technology for more leakage reduction coming up later. For both the voltage scaling and power gating techniques, TSMC provides a data retention capability that stores the data during power down and ensures the circuits function normally at wake-up. Design for Manufacturing (DFM) At the 65 nanometer technology node, process variance and pattern sensitivity are emerging as major yield influencers. The need to ensure accurate information flow between design and manufacturing is clear. Reference Flow 6.0 follows the tradition of the previous generations by offering key DFM enhancements to improve yield. A new metal fill utility increases metal density and improves metal density uniformity throughout the device. In addition, half-track wire spreading is made available for the first time, to distribute wire more evenly. A couple of earlier DFM guidelines are now part of design rules in 65nm along with the new design rules which were not there in the previous technology nodes. TSMC has proactively worked with EDA partners to embed the OPC-friendly guidelines into commercial tools, and ensured that leading EDA tools support 65nm design rules through rigorous testing with multiple testcases.
	Delivers Power Closure for Nanometer Design TSMC continues to take the lead in addressing today's most critical design challenge, power closure, with its recently announced Reference Flow 5.0. Building on four previous Reference Flow generations, Reference Flow 5.0 has enhanced the powerful dual-track methodology introduced and built around Synopsys and other EDA partners. And, for the first time, Reference Flow 5.0 creates engineering collaboration across the entire design chain, including chip and package design.
	Power Consumption Becomes a Prominent Issue New products demand greater functionality, which leads to the integration of a greater number of transistors on a single chip. This in turn results in greater dynamic power consumption. As supply voltage decreases with finer advanced technology geometries, and as thermal effects increase, power leakage in transistors increases. To effectively reduce overall power consumption, designers will have to pursue both routes to optimize both dynamic and leakage power. Reference Flow 5.0 supports both power-shutdown and voltage-scaling methodologies to reduce power consumption at both sleep mode and standby mode. Isolation cell insertion prevents leakage caused by unknown state outputs from the shutdown area. Level shifters link different power domains. Substrate bias further reduces leakage power, in addition to power shutdown and voltage scaling.
	Power Integrity Changes the Design Equation As advanced-technology supply voltages decrease, designers must compensate with lower voltage noise margins. Suddenly, power integrity issues change the design equation, as previously uniform and fixed-supply voltage assumptions become obsolete. Without addressing power integrity, there is a risk that the chip will not function as expected. Reference Flow 5.0 enables designers to perform a comprehensive IR-drop analysis that includes core logic, I/O, and package elements. In addition, the dynamic IR-drop analysis capability considers the simultaneous switching effects. Finally, the design methodology helps designers insert decoupling cells to mitigate the transient IR-drop effect.
	Integrated Chip and Package Design Packaging is no longer a "plug-and-play" component in the design chain. Package-related physical and electrical effects are now important considerations for high-integration, high-frequency designs. For the first time, Reference Flow 5.0 promotes collaboration across the design chain and bridges the previously disconnected worlds of chip and package design. Designers can now perform integrated chip- and package-routing analysis and LVS. These new capabilities boost overall productivity by shortening cycle time and eliminating the previously error-prone interaction between independent chip and package designs. The integrated chip and package IR-drop analysis and static-timing analysis further ensure the electrical performance of the design.
	Extensive EDA Collaboration By collaborating closely with our EDA partners, TSMC has effectively anticipated emerging challenges and addressed them in five successive generations of Reference Flows. As a result, TSMC is the only foundry with a comprehensive portfolio of Reference Flows covering the full spectrum of design methodology needs, from 0.25 micron to 90nm. Reference Flow 5.0 maintains the popular dual-track implementation based on Synopsys and Cadence, and includes specialty tools from Mentor and new EDA partners Apache, Atrenta, and Optimal.
	Log In to TSMC-Online Need further information about TSMC Reference Flow? Please log in to TSMC-Online, and click on "Reference Flow" under the Design Portal category.

Contact Information

Willy Chen