minPower Components
Low power datapath architectures and instantiable IP extends battery life in mobile applications and reduces power consumption for SoCs
Gate-level Extraction Techniques to Accelerate IC Design Closure and Signoff
Overview Star-RCXT™ provides unique gate-level extraction techniques to address productivity bottlenecks in physical implementation and signoff. In this webinar, our experts will demonstrate how the latest process modeling and extraction features can help you achieve accurate and faster signoff. Techniques that will be explored in detail include efficient multicore usage, multi-mode and multi-corner extraction, faster extraction for ECO validation and binary interchange with industry gold standard PrimeTime® timing signoff.
Who should attend Design engineers and managers who are familiar with gate-level extraction and would like to know more about improving physical implementation and signoff turnaround time.
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