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White Paper: Addressing Power Integrity Challenges for SoCs

Power integrity has become a crucial part of the system-on-a-chip (SoC) design flow because power-related issues can affect chip timing and even lead to complete device failure. Specifically, excessive rail voltage drop (ďIR-dropĒ) and ground bounce can create timing problems and electromigration effects that impact a chipís performance and reliability.

Analyzing a chipís power also poses difficulties. For example, an early analysis of the power grid design is critical to limiting the effects of IR-drop across the chip, but this analysis relies on basic design data that is often not available prior to the completion of the netlist.

This white paper offers power-planning and analysis methodologies to address the power integrity challenges facing designers of todayís advanced SoCís. Based on best practices developed and proven by Synopsys Professional Services in numerous leading-edge designs, the paper includes practical techniques for performing a pre-netlist IR-drop analysis, implementing a robust rail signoff flow and obtaining the best analysis results.

Click here to view an outline of the white paper.

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